github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-29 10:41:49 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: rockchip: add rga3 dt nodes to rk3588

Browse Source 
Add devicetree nodes for the RGA3 (Raster Graphics Acceleration 3)
peripheral in the RK3588.

The existing rga node refers to the RGA2-Enhanced peripheral. The RK3588
contains one RGA2-Enhanced core and two RGA3 cores. Both feature a similar
functionality of scaling, cropping and rotating of up to two input
images into one output image. Key differences of the RGA3 are:

- supports 10bit YUV output formats
- supports 8x8 tiles and FBCD as inputs and outputs
- supports BT2020 color space conversion
- max output resolution of (8192-64)x(8192-64)
- MMU can map up to 32G DDR RAM
- fully planar formats (3 planes) are not supported
- max scale up/down factor of 8 (RGA2 allows up to 16)

Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
Link: https://patch.msgid.link/20260521-spu-rga3-v7-28-3f33e8c7145f@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Sven Püschel 2026-05-21 00:44:33 +02:00 committed by Heiko Stuebner
parent eb24b60553
commit 25ee898961
1 changed files with 44 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
View File

@ -1262,6 +1262,50 @@ vpu121_mmu: iommu@fdb50800 {
#iommu-cells = <0>;
};
rga3_core0: rga@fdb60000 {
compatible = "rockchip,rk3588-rga3";
reg = <0x0 0xfdb60000 0x0 0x200>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>;
clock-names = "aclk", "hclk", "sclk";
resets = <&cru SRST_RGA3_0_CORE>, <&cru SRST_A_RGA3_0>, <&cru SRST_H_RGA3_0>;
reset-names = "core", "axi", "ahb";
power-domains = <&power RK3588_PD_RGA30>;
iommus = <&rga3_0_mmu>;
};
rga3_0_mmu: iommu@fdb60f00 {
compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
reg = <0x0 0xfdb60f00 0x0 0x100>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3588_PD_RGA30>;
};
rga3_core1: rga@fdb70000 {
compatible = "rockchip,rk3588-rga3";
reg = <0x0 0xfdb70000 0x0 0x200>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>;
clock-names = "aclk", "hclk", "sclk";
resets = <&cru SRST_RGA3_1_CORE>, <&cru SRST_A_RGA3_1>, <&cru SRST_H_RGA3_1>;
reset-names = "core", "axi", "ahb";
power-domains = <&power RK3588_PD_RGA31>;
iommus = <&rga3_1_mmu>;
};
rga3_1_mmu: iommu@fdb70f00 {
compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
reg = <0x0 0xfdb70f00 0x0 0x100>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3588_PD_RGA31>;
};
rga: rga@fdb80000 {
compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga";
reg = <0x0 0xfdb80000 0x0 0x180>;