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drm/msm/dpu: Defer SSPP allocation until CRTC check

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Currently, mapping plane to SSPP occurs during the plane check phase for
non-virtual plane case. The SSPP allocation and plane mapping occurs during
CRTC check phase for virtual plane case. Defer these SSPP operations until
CRTC check stage to unify the 2 cases, and ease later revisement for
quad-pipe change.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/711322/
Link: https://lore.kernel.org/r/20260312-msm-next-quad-pipe-split-v19-2-4ffa2b06c996@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Jun Nie 2026-03-12 16:28:11 +08:00 committed by Dmitry Baryshkov
parent febcd37fec
commit 25ee109277
2 changed files with 80 additions and 81 deletions
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25
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
View File

@ -1321,7 +1321,7 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
return false;
}
static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
static int dpu_crtc_assign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
{
int total_planes = crtc->dev->mode_config.num_total_plane;
struct drm_atomic_state *state = crtc_state->state;
@ -1334,8 +1334,6 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state
if (IS_ERR(global_state))
return PTR_ERR(global_state);
dpu_rm_release_all_sspp(global_state, crtc);
if (!crtc_state->enable)
return 0;
@ -1362,6 +1360,19 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state
return ret;
}
static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
{
struct dpu_global_state *global_state;
global_state = dpu_kms_get_global_state(crtc_state->state);
if (IS_ERR(global_state))
return PTR_ERR(global_state);
dpu_rm_release_all_sspp(global_state, crtc);
return dpu_crtc_assign_planes(crtc, crtc_state);
}
#define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE
#define MAX_HDISPLAY_SPLIT 1080
@ -1531,9 +1542,11 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
return rc;
}
if (dpu_use_virtual_planes &&
(crtc_state->planes_changed || crtc_state->zpos_changed)) {
rc = dpu_crtc_reassign_planes(crtc, crtc_state);
if (crtc_state->planes_changed || crtc_state->zpos_changed) {
if (dpu_use_virtual_planes)
rc = dpu_crtc_reassign_planes(crtc, crtc_state);
else
rc = dpu_crtc_assign_planes(crtc, crtc_state);
if (rc < 0)
return rc;
}

136
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
View File

@ -1109,65 +1109,13 @@ static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate,
static int dpu_plane_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
plane);
int ret = 0;
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
struct dpu_sw_pipe *pipe = &pstate->pipe[0];
struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];
const struct drm_crtc_state *crtc_state = NULL;
uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth;
if (new_plane_state->crtc)
crtc_state = drm_atomic_get_new_crtc_state(state,
new_plane_state->crtc);
pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
if (!pipe->sspp)
return -EINVAL;
ret = dpu_plane_atomic_check_nosspp(plane, new_plane_state, crtc_state);
if (ret)
return ret;
if (!new_plane_state->visible)
return 0;
ret = dpu_plane_split(plane, new_plane_state, crtc_state);
if (ret)
return ret;
if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
pipe->sspp,
msm_framebuffer_format(new_plane_state->fb),
max_linewidth)) {
DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT
" max_line:%u, can't use split source\n",
DRM_RECT_ARG(&pipe_cfg->src_rect),
DRM_RECT_ARG(&r_pipe_cfg->src_rect),
max_linewidth);
return -E2BIG;
}
return dpu_plane_atomic_check_sspp(plane, state, crtc_state);
}
static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
struct drm_plane_state *plane_state =
drm_atomic_get_plane_state(state, plane);
struct drm_plane_state *old_plane_state =
drm_atomic_get_old_plane_state(state, plane);
struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state);
int ret = 0;
struct drm_crtc_state *crtc_state = NULL;
int ret, i;
if (IS_ERR(plane_state))
return PTR_ERR(plane_state);
@ -1180,20 +1128,8 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
if (ret)
return ret;
if (!plane_state->visible) {
/*
* resources are freed by dpu_crtc_assign_plane_resources(),
* but clean them here.
*/
for (i = 0; i < PIPES_PER_PLANE; i++)
pstate->pipe[i].sspp = NULL;
if (!plane_state->visible)
return 0;
}
ret = dpu_plane_split(plane, plane_state, crtc_state);
if (ret)
return ret;
/*
* Force resource reallocation if the format of FB or src/dst have
@ -1208,7 +1144,6 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
msm_framebuffer_format(old_plane_state->fb) !=
msm_framebuffer_format(plane_state->fb))
crtc_state->planes_changed = true;
return 0;
}
@ -1255,9 +1190,9 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
struct dpu_global_state *global_state,
struct drm_atomic_state *state,
struct drm_plane_state *plane_state,
const struct drm_crtc_state *crtc_state,
struct drm_plane_state **prev_adjacent_plane_state)
{
const struct drm_crtc_state *crtc_state = NULL;
struct drm_plane *plane = plane_state->plane;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
struct dpu_rm_sspp_requirements reqs;
@ -1267,10 +1202,6 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
const struct msm_format *fmt;
int i, ret;
if (plane_state->crtc)
crtc_state = drm_atomic_get_new_crtc_state(state,
plane_state->crtc);
pstate = to_dpu_plane_state(plane_state);
for (i = 0; i < STAGES_PER_PLANE; i++)
prev_adjacent_pstate[i] = prev_adjacent_plane_state[i] ?
@ -1282,6 +1213,10 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
if (!plane_state->fb)
return -EINVAL;
ret = dpu_plane_split(plane, plane_state, crtc_state);
if (ret)
return ret;
fmt = msm_framebuffer_format(plane_state->fb);
reqs.yuv = MSM_FORMAT_IS_YUV(fmt);
reqs.scale = (plane_state->src_w >> 16 != plane_state->crtc_w) ||
@ -1312,14 +1247,55 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
return dpu_plane_atomic_check_sspp(plane, state, crtc_state);
}
static int dpu_plane_assign_resources(struct drm_crtc *crtc,
struct dpu_global_state *global_state,
struct drm_atomic_state *state,
struct drm_plane_state *plane_state,
const struct drm_crtc_state *crtc_state)
{
struct drm_plane *plane = plane_state->plane;
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state);
struct dpu_sw_pipe *pipe = &pstate->pipe[0];
struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];
struct dpu_plane *pdpu = to_dpu_plane(plane);
int ret;
pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
if (!pipe->sspp)
return -EINVAL;
ret = dpu_plane_split(plane, plane_state, crtc_state);
if (ret)
return ret;
if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
pipe->sspp,
msm_framebuffer_format(plane_state->fb),
dpu_kms->catalog->caps->max_linewidth)) {
DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT
" max_line:%u, can't use split source\n",
DRM_RECT_ARG(&pipe_cfg->src_rect),
DRM_RECT_ARG(&r_pipe_cfg->src_rect),
dpu_kms->catalog->caps->max_linewidth);
return -E2BIG;
}
return dpu_plane_atomic_check_sspp(plane, state, crtc_state);
}
int dpu_assign_plane_resources(struct dpu_global_state *global_state,
struct drm_atomic_state *state,
struct drm_crtc *crtc,
struct drm_plane_state **states,
unsigned int num_planes)
{
unsigned int i;
struct drm_plane_state *prev_adjacent_plane_state[STAGES_PER_PLANE] = { NULL };
const struct drm_crtc_state *crtc_state = NULL;
unsigned int i;
int ret;
for (i = 0; i < num_planes; i++) {
struct drm_plane_state *plane_state = states[i];
@ -1328,8 +1304,18 @@ int dpu_assign_plane_resources(struct dpu_global_state *global_state,
!plane_state->visible)
continue;
int ret = dpu_plane_virtual_assign_resources(crtc, global_state,
if (plane_state->crtc)
crtc_state = drm_atomic_get_new_crtc_state(state,
plane_state->crtc);
if (!dpu_use_virtual_planes)
ret = dpu_plane_assign_resources(crtc, global_state,
state, plane_state,
crtc_state);
else
ret = dpu_plane_virtual_assign_resources(crtc, global_state,
state, plane_state,
crtc_state,
prev_adjacent_plane_state);
if (ret)
return ret;
@ -1766,7 +1752,7 @@ static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
static const struct drm_plane_helper_funcs dpu_plane_virtual_helper_funcs = {
.prepare_fb = dpu_plane_prepare_fb,
.cleanup_fb = dpu_plane_cleanup_fb,
.atomic_check = dpu_plane_virtual_atomic_check,
.atomic_check = dpu_plane_atomic_check,
.atomic_update = dpu_plane_atomic_update,
};