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pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resume

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Include the NOD (N-ch Open Drain) register in the PM suspend/resume
register cache.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260413182456.811543-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2026-04-13 19:24:54 +01:00 committed by Geert Uytterhoeven
parent d0fc9f8eb2
commit 25e71db480
1 changed files with 35 additions and 2 deletions
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37
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View File

@ -323,6 +323,7 @@ struct rzg2l_pinctrl_pin_settings {
* @ien: IEN registers cache
* @smt: SMT registers cache
* @sr: SR registers cache
* @nod: NOD registers cache
* @sd_ch: SD_CH registers cache
* @eth_poc: ET_POC registers cache
* @oen: Output Enable register cache
@ -338,6 +339,7 @@ struct rzg2l_pinctrl_reg_cache {
u32 *pupd[2];
u32 *smt[2];
u32 *sr[2];
u32 *nod[2];
u8 sd_ch[2];
u8 eth_poc[2];
u8 oen;
@ -2767,6 +2769,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
if (!cache->sr[i])
return -ENOMEM;
cache->nod[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->nod[i]),
GFP_KERNEL);
if (!cache->nod[i])
return -ENOMEM;
/* Allocate dedicated cache. */
dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
sizeof(*dedicated_cache->iolh[i]),
@ -2785,6 +2792,12 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
GFP_KERNEL);
if (!dedicated_cache->sr[i])
return -ENOMEM;
dedicated_cache->nod[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
sizeof(*dedicated_cache->nod[i]),
GFP_KERNEL);
if (!dedicated_cache->nod[i])
return -ENOMEM;
}
pctrl->cache = cache;
@ -3016,7 +3029,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
for (u32 port = 0; port < nports; port++) {
bool has_iolh, has_ien, has_pupd, has_smt, has_sr;
bool has_iolh, has_ien, has_pupd, has_smt, has_sr, has_nod;
u32 off, caps;
u8 pincnt;
u64 cfg;
@ -3038,6 +3051,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
has_pupd = !!(caps & PIN_CFG_PUPD);
has_smt = !!(caps & PIN_CFG_SMT);
has_sr = !!(caps & PIN_CFG_SR);
has_nod = !!(caps & PIN_CFG_NOD);
if (suspend)
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
@ -3098,6 +3112,15 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
cache->sr[1][port]);
}
}
if (has_nod) {
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off),
cache->nod[0][port]);
if (pincnt >= 4) {
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off) + 4,
cache->nod[1][port]);
}
}
}
}
@ -3112,7 +3135,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
* port offset are close together.
*/
for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
bool has_iolh, has_ien, has_sr;
bool has_iolh, has_ien, has_sr, has_nod;
u32 off, next_off = 0;
u64 cfg, next_cfg;
u8 pincnt;
@ -3135,6 +3158,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
PIN_CFG_IOLH_C | PIN_CFG_IOLH_RZV2H));
has_ien = !!(caps & PIN_CFG_IEN);
has_sr = !!(caps & PIN_CFG_SR);
has_nod = !!(caps & PIN_CFG_NOD);
pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));
if (has_iolh) {
@ -3149,6 +3173,10 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off),
cache->sr[0][i]);
}
if (has_nod) {
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off),
cache->nod[0][i]);
}
if (pincnt >= 4) {
if (has_iolh) {
RZG2L_PCTRL_REG_ACCESS32(suspend,
@ -3165,6 +3193,11 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
pctrl->base + SR(off) + 4,
cache->sr[1][i]);
}
if (has_nod) {
RZG2L_PCTRL_REG_ACCESS32(suspend,
pctrl->base + NOD(off) + 4,
cache->nod[1][i]);
}
}
caps = 0;
}