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add L2 cache controller driver

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This commit is contained in:
hxy 2012-03-10 15:55:32 +08:00
parent ea01aa531e
commit 25acf71835
1 changed files with 41 additions and 0 deletions
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41
arch/arm/mach-rk30/common.c
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@ -5,6 +5,7 @@
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
#include <plat/sram.h>
#include <mach/board.h>
@ -12,6 +13,44 @@
#include <mach/iomux.h>
#include <mach/fiq.h>
static void __init rk30_l2_cache_init(void)
{
#ifdef CONFIG_CACHE_L2X0
u32 aux_ctrl, aux_ctrl_mask;
//Tag Ram Latency All 1-cycle
writel_relaxed(0x0, RK30_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
// Data Ram Latency [10:8] 1-cycle [6:4] 4-cycles [2:0] 2 cycles
writel_relaxed(0x031, RK30_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
/*
* 16-way associativity, parity disabled
* Way size - 32KB
*/
aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
(0x1 << 25) | // round-robin
(0x1 << 0) | // Full Line of Zero Enable
(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
(0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 32KB way-size
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
(0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
aux_ctrl_mask = ~((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
(0x1 << 25) | // round-robin
(0x1 << 0) | // Full Line of Zero Enable
(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
(0x7 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 32KB way-size
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
(0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
l2x0_init(RK30_L2C_BASE, aux_ctrl, aux_ctrl_mask);
#endif
}
void __init rk30_init_irq(void)
{
gic_init(0, IRQ_LOCALTIMER, RK30_GICD_BASE, RK30_GICC_BASE);
@ -27,6 +66,7 @@ void __init rk30_map_io(void)
rk29_setup_early_printk();
rk29_sram_init();
rk30_clock_init();
rk30_l2_cache_init();
rk30_iomux_init();
}
@ -37,3 +77,4 @@ void __init rk30_fixup(struct machine_desc *desc, struct tag *tags,
mi->bank[0].start = PLAT_PHYS_OFFSET;
mi->bank[0].size = SZ_128M;
}