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arm64/sysreg: Convert ID_ISAR0_EL1 to automatic generation

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Convert ID_ISAR0_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-23-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
James Morse 2022-11-30 17:16:21 +00:00 committed by Will Deacon
parent 5b380ae0e2
commit 258a96b25a
2 changed files with 36 additions and 9 deletions
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9
arch/arm64/include/asm/sysreg.h
View File

@ -173,7 +173,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
@ -703,14 +702,6 @@
#define ID_DFR1_EL1_MTPMU_SHIFT 0
#define ID_ISAR0_EL1_Divide_SHIFT 24
#define ID_ISAR0_EL1_Debug_SHIFT 20
#define ID_ISAR0_EL1_Coproc_SHIFT 16
#define ID_ISAR0_EL1_CmpBranch_SHIFT 12
#define ID_ISAR0_EL1_BitField_SHIFT 8
#define ID_ISAR0_EL1_BitCount_SHIFT 4
#define ID_ISAR0_EL1_Swap_SHIFT 0
#define ID_ISAR5_EL1_RDM_SHIFT 24
#define ID_ISAR5_EL1_CRC32_SHIFT 16
#define ID_ISAR5_EL1_SHA2_SHIFT 12

36
arch/arm64/tools/sysreg
View File

@ -223,6 +223,42 @@ Enum 3:0 CMaintVA
EndEnum
EndSysreg
Sysreg ID_ISAR0_EL1 3 0 0 2 0
Res0 63:28
Enum 27:24 Divide
0b0000 NI
0b0001 xDIV_T32
0b0010 xDIV_A32
EndEnum
Enum 23:20 Debug
0b0000 NI
0b0001 IMP
EndEnum
Enum 19:16 Coproc
0b0000 NI
0b0001 MRC
0b0010 MRC2
0b0011 MRRC
0b0100 MRRC2
EndEnum
Enum 15:12 CmpBranch
0b0000 NI
0b0001 IMP
EndEnum
Enum 11:8 BitField
0b0000 NI
0b0001 IMP
EndEnum
Enum 7:4 BitCount
0b0000 NI
0b0001 IMP
EndEnum
Enum 3:0 Swap
0b0000 NI
0b0001 IMP
EndEnum
EndSysreg
Sysreg ID_MMFR4_EL1 3 0 0 2 6
Res0 63:32
Enum 31:28 EVT