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drm/i915/pps: only touch the vlv_ members on VLV/CHV

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While the struct intel_pps vlv_pps_pipe and vlv_active_pipe members are
only relevant for VLV/CHV, we still initialize them on all platforms and
check them on BXT/GLK. Wrap all access inside VLV/CHV checks for
consistency.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/158c7b30e56d22aa3f9c9e51e87b9d89687d74d5.1726681620.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2024-09-18 20:47:43 +03:00
parent 66bdc6a61e
commit 254b109d65
2 changed files with 9 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -6867,8 +6867,6 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
return false;
intel_dp->reset_link_params = true;
intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
intel_dp->pps.vlv_active_pipe = INVALID_PIPE;
/* Preserve the current hw state. */
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
@ -6895,8 +6893,10 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
intel_dp_set_default_sink_rates(intel_dp);
intel_dp_set_default_max_sink_lane_count(intel_dp);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
}
intel_dp_aux_init(intel_dp);
intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;

11
drivers/gpu/drm/i915/display/intel_pps.c
View File

@ -472,16 +472,17 @@ void intel_pps_reset_all(struct intel_display *display)
for_each_intel_dp(display->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
drm_WARN_ON(display->drm,
intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
drm_WARN_ON(display->drm,
intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
if (encoder->type != INTEL_OUTPUT_EDP)
continue;
if (DISPLAY_VER(display) >= 9)
intel_dp->pps.bxt_pps_reset = true;
else
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
else
intel_dp->pps.bxt_pps_reset = true;
}
}