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irqchip/gic-v3: Ensure change to DS is visible

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Sashiko reported missing GIC synchronization when the
FLAGS_WORKAROUND_INSECURE path modifies DS. Specifically, an immediate
read of the DS state after the write might not observe the effect of
that write, which can lead to misreporting the DS state.

Updates to the DS bit are tracked by RWP, so poll it after the write
before proceeding to read back the DS state.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://patch.msgid.link/20260930161123.46368-1-vladimir.murzin@arm.com
This commit is contained in:
Vladimir Murzin 2026-09-30 17:11:23 +01:00 committed by Thomas Gleixner
parent a5f0dc656e
commit 254772534e
1 changed files with 2 additions and 0 deletions
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2
drivers/irqchip/irq-gic-v3.c
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@ -164,6 +164,7 @@ static inline bool gic_dist_security_disabled(void)
static bool cpus_have_security_disabled __ro_after_init;
static bool cpus_have_group0 __ro_after_init;
static void gic_dist_wait_for_rwp(void);
static void __init gic_prio_init(void)
{
@ -179,6 +180,7 @@ static void __init gic_prio_init(void)
val = readl_relaxed(gic_data.dist_base + GICD_CTLR);
val |= GICD_CTLR_DS;
writel_relaxed(val, gic_data.dist_base + GICD_CTLR);
gic_dist_wait_for_rwp();
ds = gic_dist_security_disabled();
if (ds)