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pinctrl: starfive: Add StarFive JHB100 per1 controller driver
Add pinctrl driver for StarFive JHB100 SoC Peripheral-1(per1) pinctrl controller. Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com> Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com> Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Changhuang Liang
Linus Walleij
parent
d6001140c2
commit
2539dfb77e
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@ -67,6 +67,17 @@ config PINCTRL_STARFIVE_JHB100_PER0
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peripherals supporting inputs, outputs, configuring pull-up/pull-down
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and interrupts on input changes.
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config PINCTRL_STARFIVE_JHB100_PER1
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tristate "StarFive JHB100 SoC Peripheral-1 pinctrl and GPIO driver"
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depends on ARCH_STARFIVE || COMPILE_TEST
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select PINCTRL_STARFIVE_JHB100
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default ARCH_STARFIVE
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help
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Say yes here to support Peripheral-1 pin control on the StarFive JHB100 SoC.
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This also provides an interface to the GPIO pins not used by other
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peripherals supporting inputs, outputs, configuring pull-up/pull-down
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and interrupts on input changes.
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config PINCTRL_STARFIVE_JHB100_SYS0
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tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
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depends on ARCH_STARFIVE || COMPILE_TEST
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@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
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obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
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obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
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obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
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obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
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obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
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obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
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193
drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
Normal file
193
drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
Normal file
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@ -0,0 +1,193 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-1 domain
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*
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* Copyright (C) 2024 StarFive Technology Co., Ltd.
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* Author: Alex Soo <yuklin.soo@starfivetech.com>
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*
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*/
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#include <linux/platform_device.h>
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#include "pinctrl-starfive-jhb100.h"
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/* per1 pad numbers */
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#define PADNUM_PER1_GPIO_C0 0
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#define PADNUM_PER1_GPIO_C1 1
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#define PADNUM_PER1_GPIO_C2 2
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#define PADNUM_PER1_GPIO_C3 3
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#define PADNUM_PER1_GPIO_C4 4
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#define PADNUM_PER1_GPIO_C5 5
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#define PADNUM_PER1_GPIO_C6 6
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#define PADNUM_PER1_GPIO_C7 7
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#define PADNUM_PER1_GPIO_C8 8
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#define PADNUM_PER1_GPIO_C9 9
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#define PADNUM_PER1_GPIO_C10 10
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#define PADNUM_PER1_GPIO_C11 11
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#define PADNUM_PER1_GPIO_C12 12
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#define PADNUM_PER1_GPIO_C13 13
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#define PADNUM_PER1_GPIO_C14 14
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#define PADNUM_PER1_GPIO_C15 15
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#define PADNUM_PER1_GPIO_C16 16
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#define PADNUM_PER1_GPIO_C17 17
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#define PADNUM_PER1_GPIO_C18 18
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#define PADNUM_PER1_GPIO_C19 19
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#define PADNUM_PER1_GPIO_C20 20
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#define PADNUM_PER1_GPIO_C21 21
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#define PADNUM_PER1_GPIO_C22 22
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#define PADNUM_PER1_GPIO_C23 23
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#define PADNUM_PER1_GPIO_C24 24
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#define PADNUM_PER1_GPIO_C25 25
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#define PADNUM_PER1_GPIO_C26 26
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#define PADNUM_PER1_GPIO_C27 27
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#define PADNUM_PER1_GPIO_C31 31
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#define PADNUM_PER1_GPIO_C35 35
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static const struct jhb100_pin_layout_desc jhb100_per1_pl_desc[] = {
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{ .pin_start = 0, .pin_cnt = 36, .name = "gpio", .gpio_func_sel = 0 },
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{ 0xff },
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};
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static const struct config_reg_layout_desc jhb100_per1_pinctr_rldesc[] = {
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{
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.pin_start = 0,
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.pin_cnt = 32,
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.fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
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.fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
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.fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
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.fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
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.fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
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.fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
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.fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
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},
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{
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.pin_start = 32,
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.pin_cnt = 4,
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.fields[PAD_CFG_INPUT_ENABLE] = { .shift = 0, .width = 1 },
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.fields[PAD_CFG_MODE_SELECT] = { .shift = 1, .width = 2 },
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.fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
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.fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
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.fields[PAD_CFG_OPEN_DRAIN_PULL_UP_SEL] = { .shift = 5, .width = 2 },
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.fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 7, .width = 1 },
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.fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
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},
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{ 0xff },
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};
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static const struct pinvref_desc pinvref_desc_per1[] = {
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{
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/* gpioe-spi */
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.pin_grp = {
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PADNUM_PER1_GPIO_C0,
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PADNUM_PER1_GPIO_C1,
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PADNUM_PER1_GPIO_C2,
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PADNUM_PER1_GPIO_C3,
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PADNUM_PER1_GPIO_C4
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},
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.num_pins = 5,
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.range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
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},
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{
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/* gpioe-qspi0 */
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.pin_grp = {
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PADNUM_PER1_GPIO_C5,
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PADNUM_PER1_GPIO_C6,
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PADNUM_PER1_GPIO_C7,
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PADNUM_PER1_GPIO_C8,
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PADNUM_PER1_GPIO_C9,
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PADNUM_PER1_GPIO_C10,
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PADNUM_PER1_GPIO_C11
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},
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.num_pins = 7,
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.range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
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},
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{
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/* gpioe-qspi1 */
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.pin_grp = {
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PADNUM_PER1_GPIO_C12,
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PADNUM_PER1_GPIO_C13,
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PADNUM_PER1_GPIO_C14,
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PADNUM_PER1_GPIO_C15,
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PADNUM_PER1_GPIO_C16,
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PADNUM_PER1_GPIO_C17,
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PADNUM_PER1_GPIO_C18,
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PADNUM_PER1_GPIO_C19
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},
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.num_pins = 8,
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.range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
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},
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{
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/* gpioe-qspi2 */
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.pin_grp = {
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PADNUM_PER1_GPIO_C20,
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PADNUM_PER1_GPIO_C21,
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PADNUM_PER1_GPIO_C22,
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PADNUM_PER1_GPIO_C23,
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PADNUM_PER1_GPIO_C24,
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PADNUM_PER1_GPIO_C25,
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PADNUM_PER1_GPIO_C26,
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PADNUM_PER1_GPIO_C27
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},
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.num_pins = 8,
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.range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
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},
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};
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static const struct starfive_pinctrl_regs jhb100_per1_pinctrl_regs = {
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.vref = { .reg = 0x00, .pv_desc = pinvref_desc_per1,
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.num_pv = ARRAY_SIZE(pinvref_desc_per1) },
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.func_sel = { .reg = 0xbc, .width_per_pin = 2 },
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.config = 0x14,
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.output = 0xa4,
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.output_en = 0xac,
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.gpio_status = 0xb4,
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.irq_en = 0xc8,
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.irq_status = 0xd0,
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.irq_clr = 0xd8,
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.irq_trigger = 0xe0,
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.irq_level = 0xe8,
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.irq_both_edge = 0xf0,
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.irq_edge = 0xf8,
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};
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static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per1[] = {
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{ .func = "gpio", .val = 0 },
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{ .func = "i2c", .val = 1 },
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{ .func = "sfc", .val = 1 },
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{ .func = "sgpio", .val = 1,
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.max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER1_GPIO_C31) },
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{ .func = "sgpio", .val = 2,
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.max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER1_GPIO_C35) },
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{ .func = "spi", .val = 1 },
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};
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static const struct jhb100_pinctrl_domain_info jhb100_per1_pinctrl_info = {
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.name = "jhb100-per1",
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.pl_desc = jhb100_per1_pl_desc,
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.crl_desc = jhb100_per1_pinctr_rldesc,
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.regs = &jhb100_per1_pinctrl_regs,
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.fmaps = jhb100_func_maps_per1,
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.num_maps = ARRAY_SIZE(jhb100_func_maps_per1),
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};
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static const struct of_device_id jhb100_per1_pinctrl_of_match[] = {
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{
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.compatible = "starfive,jhb100-per1-pinctrl",
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.data = &jhb100_per1_pinctrl_info,
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, jhb100_per1_pinctrl_of_match);
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static struct platform_driver jhb100_per1_pinctrl_driver = {
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.probe = jhb100_pinctrl_probe,
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.driver = {
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.name = "starfive-jhb100-per1-pinctrl",
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.of_match_table = jhb100_per1_pinctrl_of_match,
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},
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};
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module_platform_driver(jhb100_per1_pinctrl_driver);
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MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-1 domain");
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MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
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MODULE_LICENSE("GPL");
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