From ce121914f38aaa59504e20a1a625e5988fc6ead4 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Wed, 15 Oct 2025 16:52:26 +0100 Subject: [PATCH 01/25] arm64: tegra: Mark Jetson Xavier NX's PHY as a wakeup source Mark the RTL8211F PHY as a wakeup source for the Jetson Xavier NX. This allows the reworked RTL8211F driver to know that the PHY is wired to wakeup capable hardware, and thus to expose WoL capabilities. Signed-off-by: Russell King (Oracle) Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi index a410fc335fa3..c0f17f8189fa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi @@ -42,6 +42,7 @@ phy: ethernet-phy@0 { interrupt-parent = <&gpio>; interrupts = ; #phy-cells = <0>; + wakeup-source; }; }; }; From 700c48a438f3bd686b6fb066ad5b14fd13ba0cf9 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Tue, 12 Aug 2025 16:24:42 -0500 Subject: [PATCH 02/25] arm64: tegra: Add Tegra186 pin controllers Add the device tree nodes for the MAIN and AON pin controllers found on the Tegra186 family of SoCs. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 5778c93af3e6..66fdcec17073 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -36,6 +36,12 @@ gpio: gpio@2200000 { interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux 0 0 140>; + }; + + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra186-pinmux"; + reg = <0x0 0x2430000 0x0 0x15000>; }; ethernet@2490000 { @@ -1274,10 +1280,16 @@ gpio_aon: gpio@c2f0000 { interrupts = ; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinmux_aon 0 0 47>; interrupt-controller; #interrupt-cells = <2>; }; + pinmux_aon: pinmux@c300000 { + compatible = "nvidia,tegra186-pinmux-aon"; + reg = <0x0 0xc300000 0x0 0x4000>; + }; + pwm4: pwm@c340000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0xc340000 0x0 0x10000>; From 0867951a1c9230074f61a045d19d76a406e20489 Mon Sep 17 00:00:00 2001 From: sheetal Date: Mon, 29 Sep 2025 16:29:30 +0530 Subject: [PATCH 03/25] arm64: tegra: Add Tegra264 audio support - Add the audio devices for the Tegra264 SoC in the tegra264.dtsi file, which includes sound, HDA and APE(Audio Processing Engine) subsystem nodes. APE subsystem includes, - I/O interfaces such as I2S, DMIC and DSPK (all the available instances). - HW accelerators such as ASRC, OPE, MVC, SFC, AMX, ADX and Mixer (all the available instances). - ADMA controller and Interrupt controllers. - Enable the audio nodes in tegra264-p3971.dtsi platform DT file. Signed-off-by: sheetal Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra264-p3971.dtsi | 106 + arch/arm64/boot/dts/nvidia/tegra264.dtsi | 3190 +++++++++++++++++ 2 files changed, 3296 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi index 6b6259b7310f..1fcfac2066ae 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi @@ -1,4 +1,110 @@ // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause / { + bus@0 { + aconnect@9000000 { + status = "okay"; + + dma-controller@9440000 { + status = "okay"; + }; + + ahub@9630000 { + status = "okay"; + + i2s@9280000 { + status = "okay"; + }; + + i2s@9290000 { + status = "okay"; + }; + + i2s@92b0000 { + status = "okay"; + }; + }; + + interrupt-controller@9960000 { + status = "okay"; + }; + }; + + hda@88090b0000 { + nvidia,model = "NVIDIA Jetson Thor AGX HDA"; + status = "okay"; + }; + }; + + sound { + status = "okay"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + <&admaif20_port>, <&admaif21_port>, <&admaif22_port>, <&admaif23_port>, + <&admaif24_port>, <&admaif25_port>, <&admaif26_port>, <&admaif27_port>, + <&admaif28_port>, <&admaif29_port>, <&admaif30_port>, <&admaif31_port>, + /* XBAR Ports */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>, + <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, + <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, + <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, + <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, + <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, + <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, + <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, + <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, + <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, + <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, + <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, + <&xbar_amx5_in1_port>, <&xbar_amx5_in2_port>, + <&xbar_amx5_in3_port>, <&xbar_amx5_in4_port>, + <&xbar_amx6_in1_port>, <&xbar_amx6_in2_port>, + <&xbar_amx6_in3_port>, <&xbar_amx6_in4_port>, + <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, + <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, + <&xbar_adx5_in_port>, <&xbar_adx6_in_port>, + <&xbar_mix_in1_port>, <&xbar_mix_in2_port>, + <&xbar_mix_in3_port>, <&xbar_mix_in4_port>, + <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, + <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, + <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, + /* HW accelerators */ + <&sfc1_out_port>, <&sfc2_out_port>, + <&sfc3_out_port>, <&sfc4_out_port>, + <&mvc1_out_port>, <&mvc2_out_port>, + <&amx1_out_port>, <&amx2_out_port>, + <&amx3_out_port>, <&amx4_out_port>, + <&amx5_out_port>, <&amx6_out_port>, + <&adx1_out1_port>, <&adx1_out2_port>, + <&adx1_out3_port>, <&adx1_out4_port>, + <&adx2_out1_port>, <&adx2_out2_port>, + <&adx2_out3_port>, <&adx2_out4_port>, + <&adx3_out1_port>, <&adx3_out2_port>, + <&adx3_out3_port>, <&adx3_out4_port>, + <&adx4_out1_port>, <&adx4_out2_port>, + <&adx4_out3_port>, <&adx4_out4_port>, + <&adx5_out1_port>, <&adx5_out2_port>, + <&adx5_out3_port>, <&adx5_out4_port>, + <&adx6_out1_port>, <&adx6_out2_port>, + <&adx6_out3_port>, <&adx6_out4_port>, + <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, + <&mix_out4_port>, <&mix_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, + /* BE I/O Ports */ + <&i2s1_port>, <&i2s2_port>, <&i2s4_port>; + + label = "NVIDIA Jetson Thor AGX APE"; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 872a69553e3c..c66ea12ef5a3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include / { @@ -49,6 +50,3163 @@ timer@8000000 { status = "disabled"; }; + aconnect@9000000 { + compatible = "nvidia,tegra264-aconnect", + "nvidia,tegra210-aconnect"; + clocks = <&bpmp TEGRA264_CLK_APE>, + <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "ape", "apb2ape"; + power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>; + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>; + + adma: dma-controller@9440000 { + compatible = "nvidia,tegra264-adma"; + reg = <0x0 0x9440000 0x0 0xb0000>; + interrupt-parent = <&agic_page0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + clocks = <&bpmp TEGRA264_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; + + tegra_ahub: ahub@9630000 { + compatible = "nvidia,tegra264-ahub"; + reg = <0x0 0x9630000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_AHUB>; + clock-names = "ahub"; + assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>; + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + /* ADMA is under AHUB range, its excluded in the defined range */ + ranges = <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>, + <0x0 0x9510000 0x0 0x9510000 0x0 0x370000>; + + tegra_i2s1: i2s@9280000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x9280000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S1>, + <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S1>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif: endpoint { + remote-endpoint = <&xbar_i2s1>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s2: i2s@9290000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x9290000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S2>, + <&bpmp TEGRA264_CLK_I2S2_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S2>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s2_cif: endpoint { + remote-endpoint = <&xbar_i2s2>; + }; + }; + + i2s2_port: port@1 { + reg = <1>; + + i2s2_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s3: i2s@92a0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92a0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S3>, + <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S3>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif: endpoint { + remote-endpoint = <&xbar_i2s3>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s4: i2s@92b0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92b0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S4>, + <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S4>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s4_cif: endpoint { + remote-endpoint = <&xbar_i2s4>; + }; + }; + + i2s4_port: port@1 { + reg = <1>; + + i2s4_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s5: i2s@92c0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92c0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S5>, + <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S5>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s5_cif: endpoint { + remote-endpoint = <&xbar_i2s5>; + }; + }; + + i2s5_port: port@1 { + reg = <1>; + + i2s5_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s6: i2s@92d0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92d0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S6>, + <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S6>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S6"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s6_cif: endpoint { + remote-endpoint = <&xbar_i2s6>; + }; + }; + + i2s6_port: port@1 { + reg = <1>; + + i2s6_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s7: i2s@92e0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92e0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S7>, + <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S7>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S7"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s7_cif: endpoint { + remote-endpoint = <&xbar_i2s7>; + }; + }; + + i2s7_port: port@1 { + reg = <1>; + + i2s7_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s8: i2s@92f0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92f0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S8>, + <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S8>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S8"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s8_cif: endpoint { + remote-endpoint = <&xbar_i2s8>; + }; + }; + + i2s8_port: port@1 { + reg = <1>; + + i2s8_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_dmic1: dmic@9300000 { + compatible = "nvidia,tegra264-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x9300000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif: endpoint { + remote-endpoint = <&xbar_dmic1>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_dmic2: dmic@9310000 { + compatible = "nvidia,tegra264-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x9310000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif: endpoint { + remote-endpoint = <&xbar_dmic2>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_dspk1: dspk@9380000 { + compatible = "nvidia,tegra264-dspk", + "nvidia,tegra186-dspk"; + reg = <0x0 0x9380000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA264_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif: endpoint { + remote-endpoint = <&xbar_dspk1>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_amx1: amx@9510000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9510000 0x0 0x10000>; + sound-name-prefix = "AMX1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1: endpoint { + remote-endpoint = <&xbar_amx1_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2: endpoint { + remote-endpoint = <&xbar_amx1_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3: endpoint { + remote-endpoint = <&xbar_amx1_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4: endpoint { + remote-endpoint = <&xbar_amx1_in4>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out: endpoint { + remote-endpoint = <&xbar_amx1_out>; + }; + }; + }; + }; + + tegra_amx2: amx@9520000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9520000 0x0 0x10000>; + sound-name-prefix = "AMX2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1: endpoint { + remote-endpoint = <&xbar_amx2_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2: endpoint { + remote-endpoint = <&xbar_amx2_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx2_in3: endpoint { + remote-endpoint = <&xbar_amx2_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx2_in4: endpoint { + remote-endpoint = <&xbar_amx2_in4>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out: endpoint { + remote-endpoint = <&xbar_amx2_out>; + }; + }; + }; + }; + + tegra_amx3: amx@9530000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9530000 0x0 0x10000>; + sound-name-prefix = "AMX3"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1: endpoint { + remote-endpoint = <&xbar_amx3_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2: endpoint { + remote-endpoint = <&xbar_amx3_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3: endpoint { + remote-endpoint = <&xbar_amx3_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4: endpoint { + remote-endpoint = <&xbar_amx3_in4>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out: endpoint { + remote-endpoint = <&xbar_amx3_out>; + }; + }; + }; + }; + + tegra_amx4: amx@9540000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9540000 0x0 0x10000>; + sound-name-prefix = "AMX4"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1: endpoint { + remote-endpoint = <&xbar_amx4_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2: endpoint { + remote-endpoint = <&xbar_amx4_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3: endpoint { + remote-endpoint = <&xbar_amx4_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4: endpoint { + remote-endpoint = <&xbar_amx4_in4>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out: endpoint { + remote-endpoint = <&xbar_amx4_out>; + }; + }; + }; + }; + + tegra_amx5: amx@9550000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9550000 0x0 0x10000>; + sound-name-prefix = "AMX5"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx5_in1: endpoint { + remote-endpoint = <&xbar_amx5_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx5_in2: endpoint { + remote-endpoint = <&xbar_amx5_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx5_in3: endpoint { + remote-endpoint = <&xbar_amx5_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx5_in4: endpoint { + remote-endpoint = <&xbar_amx5_in4>; + }; + }; + + amx5_out_port: port@4 { + reg = <4>; + + amx5_out: endpoint { + remote-endpoint = <&xbar_amx5_out>; + }; + }; + }; + }; + + tegra_amx6: amx@9560000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9560000 0x0 0x10000>; + sound-name-prefix = "AMX6"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx6_in1: endpoint { + remote-endpoint = <&xbar_amx6_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx6_in2: endpoint { + remote-endpoint = <&xbar_amx6_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx6_in3: endpoint { + remote-endpoint = <&xbar_amx6_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx6_in4: endpoint { + remote-endpoint = <&xbar_amx6_in4>; + }; + }; + + amx6_out_port: port@4 { + reg = <4>; + + amx6_out: endpoint { + remote-endpoint = <&xbar_amx6_out>; + }; + }; + }; + }; + + tegra_adx1: adx@9590000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x9590000 0x0 0x10000>; + sound-name-prefix = "ADX1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in: endpoint { + remote-endpoint = <&xbar_adx1_in>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1: endpoint { + remote-endpoint = <&xbar_adx1_out1>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2: endpoint { + remote-endpoint = <&xbar_adx1_out2>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3: endpoint { + remote-endpoint = <&xbar_adx1_out3>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4: endpoint { + remote-endpoint = <&xbar_adx1_out4>; + }; + }; + }; + }; + + tegra_adx2: adx@95a0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95a0000 0x0 0x10000>; + sound-name-prefix = "ADX2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in: endpoint { + remote-endpoint = <&xbar_adx2_in>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1: endpoint { + remote-endpoint = <&xbar_adx2_out1>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2: endpoint { + remote-endpoint = <&xbar_adx2_out2>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3: endpoint { + remote-endpoint = <&xbar_adx2_out3>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4: endpoint { + remote-endpoint = <&xbar_adx2_out4>; + }; + }; + }; + }; + + tegra_adx3: adx@95b0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95b0000 0x0 0x10000>; + sound-name-prefix = "ADX3"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in: endpoint { + remote-endpoint = <&xbar_adx3_in>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1: endpoint { + remote-endpoint = <&xbar_adx3_out1>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2: endpoint { + remote-endpoint = <&xbar_adx3_out2>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3: endpoint { + remote-endpoint = <&xbar_adx3_out3>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4: endpoint { + remote-endpoint = <&xbar_adx3_out4>; + }; + }; + }; + }; + + tegra_adx4: adx@95c0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95c0000 0x0 0x10000>; + sound-name-prefix = "ADX4"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in: endpoint { + remote-endpoint = <&xbar_adx4_in>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1: endpoint { + remote-endpoint = <&xbar_adx4_out1>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2: endpoint { + remote-endpoint = <&xbar_adx4_out2>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3: endpoint { + remote-endpoint = <&xbar_adx4_out3>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4: endpoint { + remote-endpoint = <&xbar_adx4_out4>; + }; + }; + }; + }; + + tegra_adx5: adx@95d0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95d0000 0x0 0x10000>; + sound-name-prefix = "ADX5"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx5_in: endpoint { + remote-endpoint = <&xbar_adx5_in>; + }; + }; + + adx5_out1_port: port@1 { + reg = <1>; + + adx5_out1: endpoint { + remote-endpoint = <&xbar_adx5_out1>; + }; + }; + + adx5_out2_port: port@2 { + reg = <2>; + + adx5_out2: endpoint { + remote-endpoint = <&xbar_adx5_out2>; + }; + }; + + adx5_out3_port: port@3 { + reg = <3>; + + adx5_out3: endpoint { + remote-endpoint = <&xbar_adx5_out3>; + }; + }; + + adx5_out4_port: port@4 { + reg = <4>; + + adx5_out4: endpoint { + remote-endpoint = <&xbar_adx5_out4>; + }; + }; + }; + }; + + tegra_adx6: adx@95e0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95e0000 0x0 0x10000>; + sound-name-prefix = "ADX6"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx6_in: endpoint { + remote-endpoint = <&xbar_adx6_in>; + }; + }; + + adx6_out1_port: port@1 { + reg = <1>; + + adx6_out1: endpoint { + remote-endpoint = <&xbar_adx6_out1>; + }; + }; + + adx6_out2_port: port@2 { + reg = <2>; + + adx6_out2: endpoint { + remote-endpoint = <&xbar_adx6_out2>; + }; + }; + + adx6_out3_port: port@3 { + reg = <3>; + + adx6_out3: endpoint { + remote-endpoint = <&xbar_adx6_out3>; + }; + }; + + adx6_out4_port: port@4 { + reg = <4>; + + adx6_out4: endpoint { + remote-endpoint = <&xbar_adx6_out4>; + }; + }; + }; + }; + + tegra_admaif: admaif@9610000 { + compatible = "nvidia,tegra264-admaif"; + reg = <0x0 0x9610000 0x0 0x10000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>, + <&adma 21>, <&adma 21>, + <&adma 22>, <&adma 22>, + <&adma 23>, <&adma 23>, + <&adma 24>, <&adma 24>, + <&adma 25>, <&adma 25>, + <&adma 26>, <&adma 26>, + <&adma 27>, <&adma 27>, + <&adma 28>, <&adma 28>, + <&adma 29>, <&adma 29>, + <&adma 30>, <&adma 30>, + <&adma 31>, <&adma 31>, + <&adma 32>, <&adma 32>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20", + "rx21", "tx21", + "rx22", "tx22", + "rx23", "tx23", + "rx24", "tx24", + "rx25", "tx25", + "rx26", "tx26", + "rx27", "tx27", + "rx28", "tx28", + "rx29", "tx29", + "rx30", "tx30", + "rx31", "tx31", + "rx32", "tx32"; + + interconnects = + <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; + + iommus = <&smmu1 TEGRA264_SID_APE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0: endpoint { + remote-endpoint = <&xbar_admaif0>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1: endpoint { + remote-endpoint = <&xbar_admaif1>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2: endpoint { + remote-endpoint = <&xbar_admaif2>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3: endpoint { + remote-endpoint = <&xbar_admaif3>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4: endpoint { + remote-endpoint = <&xbar_admaif4>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5: endpoint { + remote-endpoint = <&xbar_admaif5>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6: endpoint { + remote-endpoint = <&xbar_admaif6>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7: endpoint { + remote-endpoint = <&xbar_admaif7>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8: endpoint { + remote-endpoint = <&xbar_admaif8>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9: endpoint { + remote-endpoint = <&xbar_admaif9>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10: endpoint { + remote-endpoint = <&xbar_admaif10>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11: endpoint { + remote-endpoint = <&xbar_admaif11>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12: endpoint { + remote-endpoint = <&xbar_admaif12>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13: endpoint { + remote-endpoint = <&xbar_admaif13>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14: endpoint { + remote-endpoint = <&xbar_admaif14>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15: endpoint { + remote-endpoint = <&xbar_admaif15>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16: endpoint { + remote-endpoint = <&xbar_admaif16>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17: endpoint { + remote-endpoint = <&xbar_admaif17>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18: endpoint { + remote-endpoint = <&xbar_admaif18>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19: endpoint { + remote-endpoint = <&xbar_admaif19>; + }; + }; + + admaif20_port: port@14 { + reg = <0x14>; + + admaif20: endpoint { + remote-endpoint = <&xbar_admaif20>; + }; + }; + + admaif21_port: port@15 { + reg = <0x15>; + + admaif21: endpoint { + remote-endpoint = <&xbar_admaif21>; + }; + }; + + admaif22_port: port@16 { + reg = <0x16>; + + admaif22: endpoint { + remote-endpoint = <&xbar_admaif22>; + }; + }; + + admaif23_port: port@17 { + reg = <0x17>; + + admaif23: endpoint { + remote-endpoint = <&xbar_admaif23>; + }; + }; + + admaif24_port: port@18 { + reg = <0x18>; + + admaif24: endpoint { + remote-endpoint = <&xbar_admaif24>; + }; + }; + + admaif25_port: port@19 { + reg = <0x19>; + + admaif25: endpoint { + remote-endpoint = <&xbar_admaif25>; + }; + }; + + admaif26_port: port@1a { + reg = <0x1a>; + + admaif26: endpoint { + remote-endpoint = <&xbar_admaif26>; + }; + }; + + admaif27_port: port@1b { + reg = <0x1b>; + + admaif27: endpoint { + remote-endpoint = <&xbar_admaif27>; + }; + }; + + admaif28_port: port@1c { + reg = <0x1c>; + + admaif28: endpoint { + remote-endpoint = <&xbar_admaif28>; + }; + }; + + admaif29_port: port@1d { + reg = <0x1d>; + + admaif29: endpoint { + remote-endpoint = <&xbar_admaif29>; + }; + }; + + admaif30_port: port@1e { + reg = <0x1e>; + + admaif30: endpoint { + remote-endpoint = <&xbar_admaif30>; + }; + }; + + admaif31_port: port@1f { + reg = <0x1f>; + + admaif31: endpoint { + remote-endpoint = <&xbar_admaif31>; + }; + }; + }; + }; + + tegra_sfc1: sfc@9700000 { + compatible = "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg = <0x0 0x9700000 0x0 0x10000>; + sound-name-prefix = "SFC1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in: endpoint { + remote-endpoint = <&xbar_sfc1_in>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out: endpoint { + remote-endpoint = <&xbar_sfc1_out>; + }; + }; + }; + }; + + tegra_sfc2: sfc@9710000 { + compatible = "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg = <0x0 0x9710000 0x0 0x10000>; + sound-name-prefix = "SFC2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in: endpoint { + remote-endpoint = <&xbar_sfc2_in>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out: endpoint { + remote-endpoint = <&xbar_sfc2_out>; + }; + }; + }; + }; + + tegra_sfc3: sfc@9720000 { + compatible = "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg = <0x0 0x9720000 0x0 0x10000>; + sound-name-prefix = "SFC3"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in: endpoint { + remote-endpoint = <&xbar_sfc3_in>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out: endpoint { + remote-endpoint = <&xbar_sfc3_out>; + }; + }; + }; + }; + + tegra_sfc4: sfc@9730000 { + compatible = "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg = <0x0 0x9730000 0x0 0x10000>; + sound-name-prefix = "SFC4"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in: endpoint { + remote-endpoint = <&xbar_sfc4_in>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out: endpoint { + remote-endpoint = <&xbar_sfc4_out>; + }; + }; + }; + }; + + tegra_ope1: processing-engine@9780000 { + compatible = "nvidia,tegra264-ope", + "nvidia,tegra210-ope"; + reg = <0x0 0x9780000 0x0 0x10000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x9780000 0x0 0x9780000 0x0 0x30000>; + sound-name-prefix = "OPE1"; + + equalizer@9790000 { + compatible = "nvidia,tegra264-peq", + "nvidia,tegra210-peq"; + reg = <0x0 0x9790000 0x0 0x10000>; + }; + + dynamic-range-compressor@97a0000 { + compatible = "nvidia,tegra264-mbdrc", + "nvidia,tegra210-mbdrc"; + reg = <0x0 0x97a0000 0x0 0x10000>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = + <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = + <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + tegra_mvc1: mvc@9800000 { + compatible = "nvidia,tegra264-mvc", + "nvidia,tegra210-mvc"; + reg = <0x0 0x9800000 0x0 0x10000>; + sound-name-prefix = "MVC1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in: endpoint { + remote-endpoint = <&xbar_mvc1_in>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out: endpoint { + remote-endpoint = <&xbar_mvc1_out>; + }; + }; + }; + }; + + tegra_mvc2: mvc@9810000 { + compatible = "nvidia,tegra264-mvc", + "nvidia,tegra210-mvc"; + reg = <0x0 0x9810000 0x0 0x10000>; + sound-name-prefix = "MVC2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in: endpoint { + remote-endpoint = <&xbar_mvc2_in>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out: endpoint { + remote-endpoint = <&xbar_mvc2_out>; + }; + }; + }; + }; + + tegra_amixer: amixer@9820000 { + compatible = "nvidia,tegra264-amixer", + "nvidia,tegra210-amixer"; + reg = <0x0 0x9820000 0x0 0x10000>; + sound-name-prefix = "MIXER1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mix_in1: endpoint { + remote-endpoint = <&xbar_mix_in1>; + }; + }; + + port@1 { + reg = <0x1>; + + mix_in2: endpoint { + remote-endpoint = <&xbar_mix_in2>; + }; + }; + + port@2 { + reg = <0x2>; + + mix_in3: endpoint { + remote-endpoint = <&xbar_mix_in3>; + }; + }; + + port@3 { + reg = <0x3>; + + mix_in4: endpoint { + remote-endpoint = <&xbar_mix_in4>; + }; + }; + + port@4 { + reg = <0x4>; + + mix_in5: endpoint { + remote-endpoint = <&xbar_mix_in5>; + }; + }; + + port@5 { + reg = <0x5>; + + mix_in6: endpoint { + remote-endpoint = <&xbar_mix_in6>; + }; + }; + + port@6 { + reg = <0x6>; + + mix_in7: endpoint { + remote-endpoint = <&xbar_mix_in7>; + }; + }; + + port@7 { + reg = <0x7>; + + mix_in8: endpoint { + remote-endpoint = <&xbar_mix_in8>; + }; + }; + + port@8 { + reg = <0x8>; + + mix_in9: endpoint { + remote-endpoint = <&xbar_mix_in9>; + }; + }; + + port@9 { + reg = <0x9>; + + mix_in10: endpoint { + remote-endpoint = <&xbar_mix_in10>; + }; + }; + + mix_out1_port: port@a { + reg = <0xa>; + + mix_out1: endpoint { + remote-endpoint = <&xbar_mix_out1>; + }; + }; + + mix_out2_port: port@b { + reg = <0xb>; + + mix_out2: endpoint { + remote-endpoint = <&xbar_mix_out2>; + }; + }; + + mix_out3_port: port@c { + reg = <0xc>; + + mix_out3: endpoint { + remote-endpoint = <&xbar_mix_out3>; + }; + }; + + mix_out4_port: port@d { + reg = <0xd>; + + mix_out4: endpoint { + remote-endpoint = <&xbar_mix_out4>; + }; + }; + + mix_out5_port: port@e { + reg = <0xe>; + + mix_out5: endpoint { + remote-endpoint = <&xbar_mix_out5>; + }; + }; + }; + }; + + tegra_asrc: asrc@9850000 { + compatible = "nvidia,tegra264-asrc"; + reg = <0x0 0x9850000 0x0 0x10000>; + sound-name-prefix = "ASRC1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out6_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint = <&admaif0>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint = <&admaif1>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint = <&admaif2>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint = <&admaif3>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint = <&admaif4>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint = <&admaif5>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint = <&admaif6>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint = <&admaif7>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint = <&admaif8>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint = <&admaif9>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint = <&admaif10>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint = <&admaif11>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint = <&admaif12>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint = <&admaif13>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint = <&admaif14>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint = <&admaif15>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint = <&admaif16>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint = <&admaif17>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint = <&admaif18>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint = <&admaif19>; + }; + }; + + port@14 { + reg = <0x14>; + + xbar_admaif20: endpoint { + remote-endpoint = <&admaif20>; + }; + }; + + port@15 { + reg = <0x15>; + + xbar_admaif21: endpoint { + remote-endpoint = <&admaif21>; + }; + }; + + port@16 { + reg = <0x16>; + + xbar_admaif22: endpoint { + remote-endpoint = <&admaif22>; + }; + }; + + port@17 { + reg = <0x17>; + + xbar_admaif23: endpoint { + remote-endpoint = <&admaif23>; + }; + }; + + port@18 { + reg = <0x18>; + + xbar_admaif24: endpoint { + remote-endpoint = <&admaif24>; + }; + }; + + port@19 { + reg = <0x19>; + + xbar_admaif25: endpoint { + remote-endpoint = <&admaif25>; + }; + }; + + port@1a { + reg = <0x1a>; + + xbar_admaif26: endpoint { + remote-endpoint = <&admaif26>; + }; + }; + + port@1b { + reg = <0x1b>; + + xbar_admaif27: endpoint { + remote-endpoint = <&admaif27>; + }; + }; + + port@1c { + reg = <0x1c>; + + xbar_admaif28: endpoint { + remote-endpoint = <&admaif28>; + }; + }; + + port@1d { + reg = <0x1d>; + + xbar_admaif29: endpoint { + remote-endpoint = <&admaif29>; + }; + }; + + port@1e { + reg = <0x1e>; + + xbar_admaif30: endpoint { + remote-endpoint = <&admaif30>; + }; + }; + + port@1f { + reg = <0x1f>; + + xbar_admaif31: endpoint { + remote-endpoint = <&admaif31>; + }; + }; + + xbar_i2s1_port: port@20 { + reg = <0x20>; + + xbar_i2s1: endpoint { + remote-endpoint = <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@21 { + reg = <0x21>; + + xbar_i2s2: endpoint { + remote-endpoint = <&i2s2_cif>; + }; + }; + + xbar_i2s3_port: port@22 { + reg = <0x22>; + + xbar_i2s3: endpoint { + remote-endpoint = <&i2s3_cif>; + }; + }; + + xbar_i2s4_port: port@23 { + reg = <0x23>; + + xbar_i2s4: endpoint { + remote-endpoint = <&i2s4_cif>; + }; + }; + + xbar_i2s5_port: port@24 { + reg = <0x24>; + + xbar_i2s5: endpoint { + remote-endpoint = <&i2s5_cif>; + }; + }; + + xbar_i2s6_port: port@25 { + reg = <0x25>; + + xbar_i2s6: endpoint { + remote-endpoint = <&i2s6_cif>; + }; + }; + + xbar_i2s7_port: port@26 { + reg = <0x26>; + + xbar_i2s7: endpoint { + remote-endpoint = <&i2s7_cif>; + }; + }; + + xbar_i2s8_port: port@27 { + reg = <0x27>; + + xbar_i2s8: endpoint { + remote-endpoint = <&i2s8_cif>; + }; + }; + + xbar_dmic1_port: port@28 { + reg = <0x28>; + + xbar_dmic1: endpoint { + remote-endpoint = <&dmic1_cif>; + }; + }; + + xbar_dmic2_port: port@29 { + reg = <0x29>; + + xbar_dmic2: endpoint { + remote-endpoint = <&dmic2_cif>; + }; + }; + + xbar_dspk1_port: port@2a { + reg = <0x2a>; + + xbar_dspk1: endpoint { + remote-endpoint = <&dspk1_cif>; + }; + }; + + xbar_sfc1_in_port: port@2b { + reg = <0x2b>; + + xbar_sfc1_in: endpoint { + remote-endpoint = <&sfc1_cif_in>; + }; + }; + + port@2c { + reg = <0x2c>; + + xbar_sfc1_out: endpoint { + remote-endpoint = <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@2d { + reg = <0x2d>; + + xbar_sfc2_in: endpoint { + remote-endpoint = <&sfc2_cif_in>; + }; + }; + + port@2e { + reg = <0x2e>; + + xbar_sfc2_out: endpoint { + remote-endpoint = <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@2f { + reg = <0x2f>; + + xbar_sfc3_in: endpoint { + remote-endpoint = <&sfc3_cif_in>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_sfc3_out: endpoint { + remote-endpoint = <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@31 { + reg = <0x31>; + + xbar_sfc4_in: endpoint { + remote-endpoint = <&sfc4_cif_in>; + }; + }; + + port@32 { + reg = <0x32>; + + xbar_sfc4_out: endpoint { + remote-endpoint = <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@33 { + reg = <0x33>; + + xbar_mvc1_in: endpoint { + remote-endpoint = <&mvc1_cif_in>; + }; + }; + + port@34 { + reg = <0x34>; + + xbar_mvc1_out: endpoint { + remote-endpoint = <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@35 { + reg = <0x35>; + + xbar_mvc2_in: endpoint { + remote-endpoint = <&mvc2_cif_in>; + }; + }; + + port@36 { + reg = <0x36>; + + xbar_mvc2_out: endpoint { + remote-endpoint = <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@37 { + reg = <0x37>; + + xbar_amx1_in1: endpoint { + remote-endpoint = <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@38 { + reg = <0x38>; + + xbar_amx1_in2: endpoint { + remote-endpoint = <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@39 { + reg = <0x39>; + + xbar_amx1_in3: endpoint { + remote-endpoint = <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@3a { + reg = <0x3a>; + + xbar_amx1_in4: endpoint { + remote-endpoint = <&amx1_in4>; + }; + }; + + port@3b { + reg = <0x3b>; + + xbar_amx1_out: endpoint { + remote-endpoint = <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@3c { + reg = <0x3c>; + + xbar_amx2_in1: endpoint { + remote-endpoint = <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@3d { + reg = <0x3d>; + + xbar_amx2_in2: endpoint { + remote-endpoint = <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@3e { + reg = <0x3e>; + + xbar_amx2_in3: endpoint { + remote-endpoint = <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@3f { + reg = <0x3f>; + + xbar_amx2_in4: endpoint { + remote-endpoint = <&amx2_in4>; + }; + }; + + port@40 { + reg = <0x40>; + + xbar_amx2_out: endpoint { + remote-endpoint = <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@41 { + reg = <0x41>; + + xbar_amx3_in1: endpoint { + remote-endpoint = <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@42 { + reg = <0x42>; + + xbar_amx3_in2: endpoint { + remote-endpoint = <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@43 { + reg = <0x43>; + + xbar_amx3_in3: endpoint { + remote-endpoint = <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@44 { + reg = <0x44>; + + xbar_amx3_in4: endpoint { + remote-endpoint = <&amx3_in4>; + }; + }; + + port@45 { + reg = <0x45>; + + xbar_amx3_out: endpoint { + remote-endpoint = <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@46 { + reg = <0x46>; + + xbar_amx4_in1: endpoint { + remote-endpoint = <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@47 { + reg = <0x47>; + + xbar_amx4_in2: endpoint { + remote-endpoint = <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@48 { + reg = <0x48>; + + xbar_amx4_in3: endpoint { + remote-endpoint = <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@49 { + reg = <0x49>; + + xbar_amx4_in4: endpoint { + remote-endpoint = <&amx4_in4>; + }; + }; + + port@4a { + reg = <0x4a>; + + xbar_amx4_out: endpoint { + remote-endpoint = <&amx4_out>; + }; + }; + + xbar_amx5_in1_port: port@4b { + reg = <0x4b>; + + xbar_amx5_in1: endpoint { + remote-endpoint = <&amx5_in1>; + }; + }; + + xbar_amx5_in2_port: port@4c { + reg = <0x4c>; + + xbar_amx5_in2: endpoint { + remote-endpoint = <&amx5_in2>; + }; + }; + + xbar_amx5_in3_port: port@4d { + reg = <0x4d>; + + xbar_amx5_in3: endpoint { + remote-endpoint = <&amx5_in3>; + }; + }; + + xbar_amx5_in4_port: port@4e { + reg = <0x4e>; + + xbar_amx5_in4: endpoint { + remote-endpoint = <&amx5_in4>; + }; + }; + + port@4f { + reg = <0x4f>; + + xbar_amx5_out: endpoint { + remote-endpoint = <&amx5_out>; + }; + }; + + xbar_amx6_in1_port: port@50 { + reg = <0x50>; + + xbar_amx6_in1: endpoint { + remote-endpoint = <&amx6_in1>; + }; + }; + + xbar_amx6_in2_port: port@51 { + reg = <0x51>; + + xbar_amx6_in2: endpoint { + remote-endpoint = <&amx6_in2>; + }; + }; + + xbar_amx6_in3_port: port@52 { + reg = <0x52>; + + xbar_amx6_in3: endpoint { + remote-endpoint = <&amx6_in3>; + }; + }; + + xbar_amx6_in4_port: port@53 { + reg = <0x53>; + + xbar_amx6_in4: endpoint { + remote-endpoint = <&amx6_in4>; + }; + }; + + port@54 { + reg = <0x54>; + + xbar_amx6_out: endpoint { + remote-endpoint = <&amx6_out>; + }; + }; + + xbar_adx1_in_port: port@55 { + reg = <0x55>; + + xbar_adx1_in: endpoint { + remote-endpoint = <&adx1_in>; + }; + }; + + port@56 { + reg = <0x56>; + + xbar_adx1_out1: endpoint { + remote-endpoint = <&adx1_out1>; + }; + }; + + port@57 { + reg = <0x57>; + + xbar_adx1_out2: endpoint { + remote-endpoint = <&adx1_out2>; + }; + }; + + port@58 { + reg = <0x58>; + + xbar_adx1_out3: endpoint { + remote-endpoint = <&adx1_out3>; + }; + }; + + port@59 { + reg = <0x59>; + + xbar_adx1_out4: endpoint { + remote-endpoint = <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@5a { + reg = <0x5a>; + + xbar_adx2_in: endpoint { + remote-endpoint = <&adx2_in>; + }; + }; + + port@5b { + reg = <0x5b>; + + xbar_adx2_out1: endpoint { + remote-endpoint = <&adx2_out1>; + }; + }; + + port@5c { + reg = <0x5c>; + + xbar_adx2_out2: endpoint { + remote-endpoint = <&adx2_out2>; + }; + }; + + port@5d { + reg = <0x5d>; + + xbar_adx2_out3: endpoint { + remote-endpoint = <&adx2_out3>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_adx2_out4: endpoint { + remote-endpoint = <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@5f { + reg = <0x5f>; + + xbar_adx3_in: endpoint { + remote-endpoint = <&adx3_in>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_adx3_out1: endpoint { + remote-endpoint = <&adx3_out1>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_adx3_out2: endpoint { + remote-endpoint = <&adx3_out2>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_adx3_out3: endpoint { + remote-endpoint = <&adx3_out3>; + }; + }; + + port@63 { + reg = <0x63>; + + xbar_adx3_out4: endpoint { + remote-endpoint = <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@64 { + reg = <0x64>; + + xbar_adx4_in: endpoint { + remote-endpoint = <&adx4_in>; + }; + }; + + port@65 { + reg = <0x65>; + + xbar_adx4_out1: endpoint { + remote-endpoint = <&adx4_out1>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_adx4_out2: endpoint { + remote-endpoint = <&adx4_out2>; + }; + }; + + port@67 { + reg = <0x67>; + + xbar_adx4_out3: endpoint { + remote-endpoint = <&adx4_out3>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_adx4_out4: endpoint { + remote-endpoint = <&adx4_out4>; + }; + }; + + xbar_adx5_in_port: port@69 { + reg = <0x69>; + + xbar_adx5_in: endpoint { + remote-endpoint = <&adx5_in>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_adx5_out1: endpoint { + remote-endpoint = <&adx5_out1>; + }; + }; + + port@6b { + reg = <0x6b>; + + xbar_adx5_out2: endpoint { + remote-endpoint = <&adx5_out2>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_adx5_out3: endpoint { + remote-endpoint = <&adx5_out3>; + }; + }; + + port@6d { + reg = <0x6d>; + + xbar_adx5_out4: endpoint { + remote-endpoint = <&adx5_out4>; + }; + }; + + xbar_adx6_in_port: port@6e { + reg = <0x6e>; + + xbar_adx6_in: endpoint { + remote-endpoint = <&adx6_in>; + }; + }; + + port@6f { + reg = <0x6f>; + + xbar_adx6_out1: endpoint { + remote-endpoint = <&adx6_out1>; + }; + }; + + port@70 { + reg = <0x70>; + + xbar_adx6_out2: endpoint { + remote-endpoint = <&adx6_out2>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_adx6_out3: endpoint { + remote-endpoint = <&adx6_out3>; + }; + }; + + port@72 { + reg = <0x72>; + + xbar_adx6_out4: endpoint { + remote-endpoint = <&adx6_out4>; + }; + }; + + xbar_mix_in1_port: port@73 { + reg = <0x73>; + + xbar_mix_in1: endpoint { + remote-endpoint = <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@74 { + reg = <0x74>; + + xbar_mix_in2: endpoint { + remote-endpoint = <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@75 { + reg = <0x75>; + + xbar_mix_in3: endpoint { + remote-endpoint = <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@76 { + reg = <0x76>; + + xbar_mix_in4: endpoint { + remote-endpoint = <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@77 { + reg = <0x77>; + + xbar_mix_in5: endpoint { + remote-endpoint = <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@78 { + reg = <0x78>; + + xbar_mix_in6: endpoint { + remote-endpoint = <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@79 { + reg = <0x79>; + + xbar_mix_in7: endpoint { + remote-endpoint = <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@7a { + reg = <0x7a>; + + xbar_mix_in8: endpoint { + remote-endpoint = <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@7b { + reg = <0x7b>; + + xbar_mix_in9: endpoint { + remote-endpoint = <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@7c { + reg = <0x7c>; + + xbar_mix_in10: endpoint { + remote-endpoint = <&mix_in10>; + }; + }; + + port@7d { + reg = <0x7d>; + + xbar_mix_out1: endpoint { + remote-endpoint = <&mix_out1>; + }; + }; + + port@7e { + reg = <0x7e>; + + xbar_mix_out2: endpoint { + remote-endpoint = <&mix_out2>; + }; + }; + + port@7f { + reg = <0x7f>; + + xbar_mix_out3: endpoint { + remote-endpoint = <&mix_out3>; + }; + }; + + port@80 { + reg = <0x80>; + + xbar_mix_out4: endpoint { + remote-endpoint = <&mix_out4>; + }; + }; + + port@81 { + reg = <0x81>; + + xbar_mix_out5: endpoint { + remote-endpoint = <&mix_out5>; + }; + }; + + xbar_asrc_in1_port: port@82 { + reg = <0x82>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@83 { + reg = <0x83>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@84 { + reg = <0x84>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@85 { + reg = <0x85>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@86 { + reg = <0x86>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@87 { + reg = <0x87>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@88 { + reg = <0x88>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@89 { + reg = <0x89>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@8a { + reg = <0x8a>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@8b { + reg = <0x8b>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@8c { + reg = <0x8c>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@8d { + reg = <0x8d>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@8e { + reg = <0x8e>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@8f { + reg = <0x8f>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@90 { + reg = <0x90>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; + }; + }; + + agic_page0: interrupt-controller@9960000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x9961000 0x0 0x1000>, + <0x0 0x9962000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page1: interrupt-controller@9970000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x9971000 0x0 0x1000>, + <0x0 0x9972000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page2: interrupt-controller@9980000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x9981000 0x0 0x1000>, + <0x0 0x9982000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page3: interrupt-controller@9990000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x9991000 0x0 0x1000>, + <0x0 0x9992000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page4: interrupt-controller@99a0000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x99a1000 0x0 0x1000>, + <0x0 0x99a2000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page5: interrupt-controller@99b0000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x99b1000 0x0 0x1000>, + <0x0 0x99b2000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + }; + gpcdma: dma-controller@8400000 { compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma"; reg = <0x0 0x08400000 0x0 0x210000>; @@ -189,6 +3347,22 @@ pmc: pmc@c800000 { #interrupt-cells = <2>; interrupt-controller; }; + + hda@88090b0000 { + compatible = "nvidia,tegra264-hda"; + reg = <0x88 0x90b0000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>; + clock-names = "hda"; + resets = <&bpmp TEGRA264_RESET_HDA>, + <&bpmp TEGRA264_RESET_HDACODEC>; + reset-names = "hda", "hda2codec_2x"; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu3 TEGRA264_SID_HDA>; + status = "disabled"; + }; }; /* TOP_MMIO */ @@ -625,6 +3799,22 @@ psci { method = "smc"; }; + sound { + compatible = "nvidia,tegra264-audio-graph-card"; + + clocks = <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + clock-names = "pll_a", "plla_out0"; + assigned-clocks = <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>, + <&bpmp TEGRA264_CLK_AUD_MCLK>; + assigned-clock-parents = <0>, + <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From ba97758a63b78f7e494ebdfb74ba8a8af702a33a Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Wed, 11 Jun 2025 13:53:38 -0500 Subject: [PATCH 04/25] arm64: tegra: Add NVIDIA Jetson Nano 2GB Developer Kit support This devkit is very similar to P3450, except it has less RAM, no display port, and only 3 USB host ports. Derive from P3450 and disable the hardware that is unavailable. GPIO PA6 is used to control the HDMI power rail and needs to be on for hotplug detect to work. This is mapped to the 3.3V USB hub on P3450. That USB rail is not used here, so delete the regulator to avoid conflicts. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 2 + .../boot/dts/nvidia/tegra210-p3541-0000.dts | 59 +++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 171e08c94d5a..b139cbd14442 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -3,6 +3,7 @@ # Enables support for device-tree overlays DTC_FLAGS_tegra210-p2371-2180 := -@ DTC_FLAGS_tegra210-p3450-0000 := -@ +DTC_FLAGS_tegra210-p3541-0000 := -@ DTC_FLAGS_tegra186-p2771-0000 := -@ DTC_FLAGS_tegra186-p3509-0000+p3636-0001 := -@ DTC_FLAGS_tegra194-p2972-0000 := -@ @@ -19,6 +20,7 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3541-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts new file mode 100644 index 000000000000..b86e271dde0b --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra210-p3450-0000.dts" + +/ { + model = "NVIDIA Jetson Nano 2GB Developer Kit"; + compatible = "nvidia,p3541-0000", "nvidia,p3450-0000", "nvidia,tegra210"; + + memory@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + host1x@50000000 { + sor@54540000 { + status = "disabled"; + }; + + dpaux@545c0000 { + status = "disabled"; + }; + }; + + padctl@7009f000 { + ports { + usb2-1 { + vbus-supply = <&vdd_hub_5v0>; + }; + + usb2-2 { + vbus-supply = <&vdd_hub_5v0>; + }; + + usb3-0 { + /delete-property/ vbus-supply; + }; + }; + }; + + regulator-vdd-hdmi-5v0 { + gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /delete-node/ regulator-vdd-hub-3v3; + + vdd_hub_5v0: regulator-vdd-hub-5v0 { + compatible = "regulator-fixed"; + + regulator-name = "VDD_HUB_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vdd_5v0_sys>; + }; +}; From 21ef26d0e71f053e809926d45b86b0afbc3686bb Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 9 Oct 2025 16:22:54 +0200 Subject: [PATCH 05/25] arm64: tegra: Add pinctrl definitions for pcie-ep nodes When the PCIe controller is running in endpoint mode, the controller initialization is triggered by a PERST# (PCIe reset) GPIO deassertion. The driver has configured an IRQ to trigger when the PERST# GPIO changes state. Without the pinctrl definition, we do not get an IRQ when PERST# is deasserted, so the PCIe controller never gets initialized. Add the missing definitions, so that the controller actually gets initialized. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition") Signed-off-by: Niklas Cassel Reviewed-by: Manikanta Maddireddy [treding@nvidia.com: add blank lines to separate blocks] Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 61 ++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index df034dbb8285..5657045c53d9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra234"; @@ -127,6 +128,56 @@ gpio: gpio@2200000 { pinmux: pinmux@2430000 { compatible = "nvidia,tegra234-pinmux"; reg = <0x0 0x2430000 0x0 0x19100>; + + pex_rst_c4_in_state: pinmux-pex-rst-c4-in { + pex_rst { + nvidia,pins = "pex_l4_rst_n_pl1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pex_rst_c5_in_state: pinmux-pex-rst-c5-in { + pex_rst { + nvidia,pins = "pex_l5_rst_n_paf1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pex_rst_c6_in_state: pinmux-pex-rst-c6-in { + pex_rst { + nvidia,pins = "pex_l6_rst_n_paf3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pex_rst_c7_in_state: pinmux-pex-rst-c7-in { + pex_rst { + nvidia,pins = "pex_l7_rst_n_pag1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pex_rst_c10_in_state: pinmux-pex-rst-c10-in { + pex_rst { + nvidia,pins = "pex_l10_rst_n_pag7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; }; gpcdma: dma-controller@2600000 { @@ -4630,6 +4681,8 @@ pcie-ep@140e0000 { <&bpmp TEGRA234_RESET_PEX2_CORE_10>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c10_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; @@ -4881,6 +4934,8 @@ pcie-ep@14160000 { <&bpmp TEGRA234_RESET_PEX0_CORE_4>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c4_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; nvidia,bpmp = <&bpmp 4>; @@ -5023,6 +5078,8 @@ pcie-ep@141a0000 { <&bpmp TEGRA234_RESET_PEX1_CORE_5>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c5_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; @@ -5115,6 +5172,8 @@ pcie-ep@141c0000 { <&bpmp TEGRA234_RESET_PEX1_CORE_6>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c6_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; @@ -5207,6 +5266,8 @@ pcie-ep@141e0000 { <&bpmp TEGRA234_RESET_PEX2_CORE_7>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c7_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; From 8911ee2543663588480d762184e00331cc2f008f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 4 Nov 2025 14:22:04 +0100 Subject: [PATCH 06/25] arm64: tegra: Move HDA into the correct bus HDA is part of the DISP_USB bus, so move it into that and drop the address prefix accordingly. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra264-p3971.dtsi | 4 ++- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 32 +++++++++---------- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi index 1fcfac2066ae..b1bd4ee7aee3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi @@ -29,8 +29,10 @@ interrupt-controller@9960000 { status = "okay"; }; }; + }; - hda@88090b0000 { + bus@8800000000 { + hda@90b0000 { nvidia,model = "NVIDIA Jetson Thor AGX HDA"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index c66ea12ef5a3..f137565da804 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3347,22 +3347,6 @@ pmc: pmc@c800000 { #interrupt-cells = <2>; interrupt-controller; }; - - hda@88090b0000 { - compatible = "nvidia,tegra264-hda"; - reg = <0x88 0x90b0000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>; - clock-names = "hda"; - resets = <&bpmp TEGRA264_RESET_HDA>, - <&bpmp TEGRA264_RESET_HDACODEC>; - reset-names = "hda", "hda2codec_2x"; - interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, - <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu3 TEGRA264_SID_HDA>; - status = "disabled"; - }; }; /* TOP_MMIO */ @@ -3716,6 +3700,22 @@ smmu3: iommu@6000000 { #iommu-cells = <1>; dma-coherent; }; + + hda@90b0000 { + compatible = "nvidia,tegra264-hda"; + reg = <0x0 0x90b0000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>; + clock-names = "hda"; + resets = <&bpmp TEGRA264_RESET_HDA>, + <&bpmp TEGRA264_RESET_HDACODEC>; + reset-names = "hda", "hda2codec_2x"; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu3 TEGRA264_SID_HDA>; + status = "disabled"; + }; }; /* UPHY MMIO */ From dc3ec7cbe933b11280272cc40236a9763a5316e9 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 16 Oct 2025 10:41:52 +0300 Subject: [PATCH 07/25] arm64: tegra: Drop redundant clock and reset names from TSEC node Clock and reset names are not needed if node contains only one clock and one reset. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 402b0ede1472..9ca603101436 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -183,9 +183,7 @@ tsec@54100000 { reg = <0x0 0x54100000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_TSEC>; - clock-names = "tsec"; resets = <&tegra_car 83>; - reset-names = "tsec"; status = "disabled"; }; From f797e587eb8bb7a8f11482b24c46e3359d8a9ffe Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 22 Oct 2025 17:20:41 +0300 Subject: [PATCH 08/25] arm64: tegra: Move avdd-dsi-csi-supply into CSI node avdd-dsi-csi-supply belongs in CSI node, not VI. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Tested-by: Luca Ceresoli # tegra20, parallel camera Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 4 ++-- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 584461f3a619..4a64fe510f03 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -20,10 +20,10 @@ dpaux@54040000 { vi@54080000 { status = "okay"; - avdd-dsi-csi-supply = <&vdd_dsi_csi>; - csi@838 { status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index ec0e84cb83ef..f1d2606d9808 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -64,10 +64,10 @@ dpaux@54040000 { vi@54080000 { status = "okay"; - avdd-dsi-csi-supply = <&vdd_sys_1v2>; - csi@838 { status = "okay"; + + avdd-dsi-csi-supply = <&vdd_sys_1v2>; }; }; From b1806f2b4e781b010101f531e75bf8eda9aabff0 Mon Sep 17 00:00:00 2001 From: Shubhi Garg Date: Tue, 7 Oct 2025 13:57:36 +0000 Subject: [PATCH 09/25] arm64: tegra: Add device-tree node for NVVRS RTC Add NVIDIA VRS (Voltage Regulator Specification) RTC device tree node for Tegra234 P3701 and P3767 platforms. Assign VRS RTC as primary RTC (rtc0). Signed-off-by: Shubhi Garg Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi | 11 +++++++++++ arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 15 +++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi index 9086a0d010e5..58bf55c0e414 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi @@ -8,6 +8,7 @@ / { aliases { mmc0 = "/bus@0/mmc@3460000"; mmc1 = "/bus@0/mmc@3400000"; + rtc0 = "/bpmp/i2c/pmic@3c"; }; bus@0 { @@ -170,6 +171,16 @@ bpmp { i2c { status = "okay"; + pmic@3c { + compatible = "nvidia,vrs-10"; + reg = <0x3c>; + interrupt-parent = <&pmc>; + /* VRS Wake ID is 24 */ + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + }; + thermal-sensor@4c { compatible = "ti,tmp451"; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi index 84db7132e8fc..ab391a71c3d3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi @@ -7,6 +7,7 @@ / { aliases { mmc0 = "/bus@0/mmc@3400000"; + rtc0 = "/bpmp/i2c/pmic@3c"; }; bus@0 { @@ -121,6 +122,20 @@ pmc@c360000 { }; }; + bpmp { + i2c { + pmic@3c { + compatible = "nvidia,vrs-10"; + reg = <0x3c>; + interrupt-parent = <&pmc>; + /* VRS Wake ID is 24 */ + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; From 60bb55de5d6ccdf07a9389cb856661753c0f9713 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Tue, 21 Oct 2025 22:13:22 -0500 Subject: [PATCH 10/25] arm64: tegra: Add ACTMON on Tegra210 This enables the action monitor to facilitate dynamic frequency scaling. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 9ca603101436..1b3fc151e49d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -483,6 +483,18 @@ flow-controller@60007000 { reg = <0x0 0x60007000 0x0 0x1000>; }; + actmon@6000c800 { + compatible = "nvidia,tegra210-actmon", "nvidia,tegra124-actmon"; + reg = <0x0 0x6000c800 0x0 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_ACTMON>, + <&tegra_car TEGRA210_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car 119>; + reset-names = "actmon"; + #cooling-cells = <2>; + }; + gpio: gpio@6000d000 { compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; From 3cad4369399a31277e9e20de723c665b30cba574 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Tue, 21 Oct 2025 22:13:23 -0500 Subject: [PATCH 11/25] arm64: tegra: Add interconnect properties for Tegra210 Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe the hardware interconnection. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 1b3fc151e49d..c196ceed9350 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -200,6 +200,19 @@ dc@54200000 { nvidia,outputs = <&dsia &dsib &sor0 &sor1>; nvidia,head = <0>; + + interconnects = <&mc TEGRA210_MC_DISPLAY0A &emc>, + <&mc TEGRA210_MC_DISPLAY0B &emc>, + <&mc TEGRA210_MC_DISPLAY0C &emc>, + <&mc TEGRA210_MC_DISPLAYHC &emc>, + <&mc TEGRA210_MC_DISPLAYD &emc>, + <&mc TEGRA210_MC_DISPLAYT &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor", + "wind", + "wint"; }; dc@54240000 { @@ -215,6 +228,15 @@ dc@54240000 { nvidia,outputs = <&dsia &dsib &sor0 &sor1>; nvidia,head = <1>; + + interconnects = <&mc TEGRA210_MC_DISPLAY0AB &emc>, + <&mc TEGRA210_MC_DISPLAY0BB &emc>, + <&mc TEGRA210_MC_DISPLAY0CB &emc>, + <&mc TEGRA210_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; }; dsia: dsi@54300000 { @@ -988,6 +1010,7 @@ mc: memory-controller@70019000 { #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; emc: external-memory-controller@7001b000 { @@ -999,6 +1022,7 @@ emc: external-memory-controller@7001b000 { clock-names = "emc"; interrupts = ; nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; #cooling-cells = <2>; }; From 654427e0b9b755d968bfd4147fc249ba1bd56ea9 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Tue, 21 Oct 2025 22:13:24 -0500 Subject: [PATCH 12/25] arm64: tegra: Add OPP tables on Tegra210 This adds OPP tables for ACTMON and EMC, enabling dynamic frequency scaling for system memory. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra210-peripherals-opp.dtsi | 135 ++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 7 + 2 files changed, 142 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi new file mode 100644 index 000000000000..bf2527d73793 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + /* EMC DVFS OPP table */ + emc_icc_dvfs_opp_table: opp-table-dvfs0 { + compatible = "operating-points-v2"; + + opp-40800000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp-68000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp-102000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp-204000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0007>; + opp-suspend; + }; + + opp-408000000-812 { + opp-microvolt = <812000 812000 1150000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0003>; + }; + + opp-665600000-825 { + opp-microvolt = <825000 825000 1150000>; + opp-hz = /bits/ 64 <665600000>; + opp-supported-hw = <0x0003>; + }; + + opp-800000000-825 { + opp-microvolt = <825000 825000 1150000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x0003>; + }; + + opp-1065600000-837 { + opp-microvolt = <837000 837000 1150000>; + opp-hz = /bits/ 64 <1065600000>; + opp-supported-hw = <0x0003>; + }; + + opp-1331200000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <1331200000>; + opp-supported-hw = <0x0003>; + }; + + opp-1600000000-887 { + opp-microvolt = <887000 887000 1150000>; + opp-hz = /bits/ 64 <1600000000>; + opp-supported-hw = <0x0007>; + }; + }; + + /* EMC bandwidth OPP table */ + emc_bw_dfs_opp_table: opp-table-dvfs1 { + compatible = "operating-points-v2"; + + opp-40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <652800>; + }; + + opp-68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <1088000>; + }; + + opp-102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <1632000>; + }; + + opp-204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0007>; + opp-peak-kBps = <3264000>; + opp-suspend; + }; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <6528000>; + }; + + opp-665600000 { + opp-hz = /bits/ 64 <665600000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <10649600>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12800000>; + }; + + opp-1065600000 { + opp-hz = /bits/ 64 <1065600000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <17049600>; + }; + + opp-1331200000 { + opp-hz = /bits/ 64 <1331200000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <21299200>; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-supported-hw = <0x0007>; + opp-peak-kBps = <25600000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index c196ceed9350..44af2760a172 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -9,6 +9,8 @@ #include #include +#include "tegra210-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra210"; interrupt-parent = <&lic>; @@ -514,6 +516,9 @@ actmon@6000c800 { clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA210_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; #cooling-cells = <2>; }; @@ -1022,6 +1027,8 @@ emc: external-memory-controller@7001b000 { clock-names = "emc"; interrupts = ; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + #interconnect-cells = <0>; #cooling-cells = <2>; }; From cddc94edf1979b5afacf9bf6f3709585baa36b78 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:52 +0200 Subject: [PATCH 13/25] arm64: tegra: Add default GIC address cells on Tegra132 Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: tegra132.dtsi:32.3-41: Warning (interrupt_map): /pcie@1003000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@50041000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 5bcccfef3f7f..93208eb72cb0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -175,6 +175,7 @@ i2c-bus { gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x50041000 0x0 0x1000>, From 311cbb9c130e2af184f5e0dc49bd891b020b6596 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:53 +0200 Subject: [PATCH 14/25] arm64: tegra: Add default GIC address cells on Tegra186 Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: tegra186.dtsi:1355.3-41: Warning (interrupt_map): /pcie@10003000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@3881000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 66fdcec17073..b00630451909 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1179,6 +1179,7 @@ fuse@3820000 { gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x03881000 0x0 0x1000>, From 7d14d53bc81079d55cc5df25f1975d28e9c2b640 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:54 +0200 Subject: [PATCH 15/25] arm64: tegra: Add default GIC address cells on Tegra194 Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: tegra194.dtsi:2391.4-42: Warning (interrupt_map): /bus@0/pcie@14100000:interrupt-map: Missing property '#address-cells' in node /bus@0/interrupt-controller@3881000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 1399342f23e1..b782f8db1288 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1331,6 +1331,7 @@ fuse@3820000 { gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x03881000 0x0 0x1000>, From 6db753b9211082e11454cd6f4b2de308967b57bf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:55 +0200 Subject: [PATCH 16/25] arm64: tegra: Add default GIC address cells on Tegra210 Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: tegra210.dtsi:31.3-41: Warning (interrupt_map): /pcie@1003000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@50041000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 44af2760a172..83f825985530 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -431,6 +431,7 @@ i2c@546c0000 { gic: interrupt-controller@50041000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x50041000 0x0 0x1000>, From feee7f5ae275dc6573f029824736ef61158cdb77 Mon Sep 17 00:00:00 2001 From: Nino Zhang Date: Fri, 22 Aug 2025 18:41:11 +0800 Subject: [PATCH 17/25] arm64: tegra: Fix APB DMA controller node name The APB DMA controller node is currently named "dma@60020000", but according to the DT bindings the node name should be "dma-controller". Update the node name to match the binding and fix dtbs_check warnings. Signed-off-by: Nino Zhang Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 93208eb72cb0..26cd11a8a4a1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -272,7 +272,7 @@ gpio: gpio@6000d000 { interrupt-controller; }; - apbdma: dma@60020000 { + apbdma: dma-controller@60020000 { compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; reg = <0x0 0x60020000 0x0 0x1400>; interrupts = , diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 83f825985530..ba0b52e4aec9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -540,7 +540,7 @@ gpio: gpio@6000d000 { interrupt-controller; }; - apbdma: dma@60020000 { + apbdma: dma-controller@60020000 { compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; reg = <0x0 0x60020000 0x0 0x1400>; interrupts = , From 961e69a5dc78491f6c8402c6016c5d6e3c1f11f7 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Sat, 16 Aug 2025 01:03:21 -0500 Subject: [PATCH 18/25] arm64: tegra: Enable NVDEC and NVENC on Tegra210 The other engines are already enabled, finish filling out the media engine nodes and power domains. Signed-off-by: Aaron Kling Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 28 ++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ba0b52e4aec9..96b6b9bc0a7f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -299,13 +299,25 @@ dsib: dsi@54400000 { nvdec@54480000 { compatible = "nvidia,tegra210-nvdec"; reg = <0x0 0x54480000 0x0 0x00040000>; - status = "disabled"; + clocks = <&tegra_car TEGRA210_CLK_NVDEC>; + clock-names = "nvdec"; + resets = <&tegra_car 194>; + reset-names = "nvdec"; + + iommus = <&mc TEGRA_SWGROUP_NVDEC>; + power-domains = <&pd_nvdec>; }; nvenc@544c0000 { compatible = "nvidia,tegra210-nvenc"; reg = <0x0 0x544c0000 0x0 0x00040000>; - status = "disabled"; + clocks = <&tegra_car TEGRA210_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&tegra_car 219>; + reset-names = "nvenc"; + + iommus = <&mc TEGRA_SWGROUP_NVENC>; + power-domains = <&pd_nvenc>; }; tsec@54500000 { @@ -932,6 +944,18 @@ pd_audio: aud { #power-domain-cells = <0>; }; + pd_nvenc: mpe { + clocks = <&tegra_car TEGRA210_CLK_NVENC>; + resets = <&tegra_car 219>; + #power-domain-cells = <0>; + }; + + pd_nvdec: nvdec { + clocks = <&tegra_car TEGRA210_CLK_NVDEC>; + resets = <&tegra_car 194>; + #power-domain-cells = <0>; + }; + pd_sor: sor { clocks = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, From 28f917d1a84afc86853513351cb0320844f51265 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Sun, 3 Aug 2025 22:14:30 -0500 Subject: [PATCH 19/25] arm64: tegra: Add reserved-memory node for P3450 The Tegra210 L4T bootloader RAM training will corrupt the in-RAM kernel DT if no reserved-memory node exists. This prevents said bootloader from being able to boot a kernel without this node, unless a chainloaded bootloader loads the DT. Add the node to eliminate the requirement for extra boot stages. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index f1d2606d9808..99b75a6b2dfe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -22,6 +22,12 @@ chosen { stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x1 0x0>; From 3da2ea1933c6372e22d2a536bbe86dd3e7d09121 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Sun, 3 Aug 2025 22:14:31 -0500 Subject: [PATCH 20/25] arm64: tegra: Add reserved-memory node for P2180 The Tegra210 L4T bootloader RAM training will corrupt the in-RAM kernel DT if no reserved-memory node exists. This prevents said bootloader from being able to boot a kernel without this node, unless a chainloaded bootloader loads the DT. Add the node to eliminate the requirement for extra boot stages. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index e07aeeee3586..9ee7952af799 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -18,6 +18,12 @@ chosen { stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x1 0x0>; From 11c52a226ef535de2ec9b09f2811eced4b9931b2 Mon Sep 17 00:00:00 2001 From: Haotien Hsu Date: Mon, 11 Aug 2025 15:45:56 +0800 Subject: [PATCH 21/25] arm64: tegra: Add interrupts for Tegra234 USB wake events Add interrupts for Tegra234 USB wake events to support the USB wake-up function. Signed-off-by: Haotien Hsu Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 5657045c53d9..827dbb420826 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3327,8 +3327,15 @@ usb@3610000 { <0x0 0x03650000 0x0 0x10000>; reg-names = "hcd", "fpci", "bar2"; - interrupts = , - ; + interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 77 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 78 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 79 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 80 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 81 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, <&bpmp TEGRA234_CLK_XUSB_FALCON>, From 172de4d681eadce124a2e0a0b881ac139afac584 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Mon, 30 Jun 2025 09:48:43 +0100 Subject: [PATCH 22/25] arm64: tegra: Add Tegra210 NVJPG power-domain node Add the NVJPG power-domain node in order to support the NVJPG accelerator in Tegra210 platforms. Reviewed-by: Mikko Perttunen Signed-off-by: Diogo Ivo Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 96b6b9bc0a7f..180080d4e68b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1009,6 +1009,12 @@ pd_xusbhost: xusbc { resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; #power-domain-cells = <0>; }; + + pd_nvjpg: nvjpg { + clocks = <&tegra_car TEGRA210_CLK_NVJPG>; + resets = <&tegra_car 195>; + #power-domain-cells = <0>; + }; }; }; From 7beff596dd375fc894173090a9b1b8eea1a83e38 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Mon, 30 Jun 2025 09:48:44 +0100 Subject: [PATCH 23/25] arm64: tegra: Add NVJPG node for Tegra210 platforms The Tegra X1 chip contains a NVJPG accelerator capable of encoding/decoding JPEG files in hardware. Complete its DT node and enable it. Reviewed-by: Mikko Perttunen Signed-off-by: Diogo Ivo Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 180080d4e68b..709da31d5785 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -275,7 +275,13 @@ vic@54340000 { nvjpg@54380000 { compatible = "nvidia,tegra210-nvjpg"; reg = <0x0 0x54380000 0x0 0x00040000>; - status = "disabled"; + clocks = <&tegra_car TEGRA210_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&tegra_car 195>; + reset-names = "nvjpg"; + + iommus = <&mc TEGRA_SWGROUP_NVJPG>; + power-domains = <&pd_nvjpg>; }; dsib: dsi@54400000 { From a72c3372ad6301705ccfdf463e32a2fc888eb173 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Mon, 26 May 2025 20:22:26 -0500 Subject: [PATCH 24/25] arm64: tegra: Set USB Micro-B port to OTG mode on P3450 The USB Micro-B port on p3450 is capable of OTG and doesn't need to be hardcoded to peripheral. No other supported Tegra device is set up like this, so align for consistency. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 99b75a6b2dfe..d78b9bd45df6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -526,7 +526,7 @@ pcie-6 { ports { usb2-0 { status = "okay"; - mode = "peripheral"; + mode = "otg"; usb-role-switch; vbus-supply = <&vdd_5v0_usb>; From 0936fa80150ef9121c6a4340fa2369bc9f16a520 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Tue, 13 May 2025 16:10:54 -0500 Subject: [PATCH 25/25] arm64: tegra: Remove OTG ID GPIO from Jetson TX2 NX The P3509 carrier board does not connect the ID GPIO. Prior to this, the GPIO role switch driver could not detect the mode of the OTG port. Signed-off-by: Aaron Kling Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 5f3f572ecea9..d9aafe053112 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -671,7 +671,6 @@ connector { vbus-gpios = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_LOW>; - id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; }; };