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arm64: tegra: Device tree changes for v6.19-rc1
This contains a bunch of additions and improvements for older devices. Tegra210 devices now have empty reserved-memory nodes to improve inter- operability with certain bootloaders. These chips now also support more multimedia engines. A new variant of the Jetson Nano is also added. Jetson TX2 sees some improvements. PCI endpoint mode is improved for Tegra234 so that reset interrupts are properly routed. A new RTC device is added starting with Orin. Rounding things off is a flurry of small fixes for DT validation and USB OTG mode. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmkYPjwACgkQ3SOs138+ s6FRXQ//Wvj9R+OgSu1egYc2CGPkM5LHxCWnqf7r80EbW020Vp9WuiFPJjsNgBpf nICaKYS5Yc4JuN1ayqa8YjNhjTy7FuuVMszMPQ+q0MsjHXYbA6N4ubNMwKfQdWm7 KGI2aAm3/SVYSBIjBsU9hNbkRYh165izxOlga5mC3ZzBIkifMnxjMLPUtNedOpq2 pxXxrCZXrZ0WfVFnULOyQJ6kdDrpTh1HELPBUzCI8yCioU8JoG7zZz/llx3f0f07 zp+pIEacuwzYL0LR0frTUA9pENXHqa5ttq5VS8l2LWCEGkfc28aodu26/mvcZcV9 c6UOKrqwj9e7+AyR+tFKq8/w0CRenyuU9oRnr1DrBSKnpowc9kz8V9pyoisbd8MM u7ZehhFajZVg6QEPXkjF5iEWLj6zWwRrtQbmDrRV9FD35GA12uNyfgQe1p1M7mwE AuzRKS5hKosz8vZ/GINI+nQ8mXsWZTzDMN0QccPUJ37zlbh9leUIBY8n2Q7rGekO sOD1DS8Jivy3XSWl9gJ0OWdXoB2kEYzgbC2O6hV+46WPb6DQNWK8A9uZGs7oqJ17 L8dGYzFaELas/RKyjxU34XqPwsAYgjrVzpAK5kszqGP+W7FaVdgt9s4/dKVKmv5D 1m92my3vaOsGoxIt2ubSOb+hhUBK4yah5Sad5vm1JZaLkPSSuyw= =y8B/ -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgi1EACgkQmmx57+YA GNm/DxAAkkP1d+cxi4q/sHLNjIG315rRnah9nQ6CIdG8UamcJEhuqKhw/aCR0UXd 2oeMfOEf/u0epNyRd+zqh9aTwI1cwLgRyFQVGp0+i4e6cVlDhZHqJMpAbCe3+0vk sQ3BoVqyLSe7svmBbjedVWMlia9kufZGxhEuOhQz2uYHjrVAocvBuIrh17wEBS6t zjdVI7fpD1zLVSEQv4LuaiZadjyb/PoEATaBujbBskSw9K3oaCv+y6T0u1aCppBL 4xVcARRblCTdxbSr8R3oQICKZTNLYHc7u+10eiDMZbTUfc40pHZe32HUdNcbI+G4 LsHg5SmrDi8ZLgZs2ZCm7a33QH5QMbD42K0jfFdeQNXu/iht4b3WjfjUaLkSSUF/ SIt6bI03Lmle9drIENThKZX7WpGQ7ejHujkRHJuWU7oJdab/tIT+3t4lfrOf+RLo cfLLzobi1GgNBstUJ14N7VsvEJn0c0nuNVTxfNlzmrzQO0ou4Pvq2u8nDYZ9eSwl T6Mray1XGLOyxYwtAz3clupwqitaiYQ8/mviFz2Yv26t7gCMJw2tEUSWTcvy8/mE 24l4FZ4nYONl/oyeKT8uqFHHUQ9Yhcqmp5b6dpHgN9vB3s/IqEoPzS1tF+PdDVHX I982r+UFJ1Zlo+TacJXiOLviMHIvPa9VloUlyNaQ7RFxfH/9aO8= =RdSU -----END PGP SIGNATURE----- Merge tag 'tegra-for-6.19-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v6.19-rc1 This contains a bunch of additions and improvements for older devices. Tegra210 devices now have empty reserved-memory nodes to improve inter- operability with certain bootloaders. These chips now also support more multimedia engines. A new variant of the Jetson Nano is also added. Jetson TX2 sees some improvements. PCI endpoint mode is improved for Tegra234 so that reset interrupts are properly routed. A new RTC device is added starting with Orin. Rounding things off is a flurry of small fixes for DT validation and USB OTG mode. * tag 'tegra-for-6.19-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits) arm64: tegra: Remove OTG ID GPIO from Jetson TX2 NX arm64: tegra: Set USB Micro-B port to OTG mode on P3450 arm64: tegra: Add NVJPG node for Tegra210 platforms arm64: tegra: Add Tegra210 NVJPG power-domain node arm64: tegra: Add interrupts for Tegra234 USB wake events arm64: tegra: Add reserved-memory node for P2180 arm64: tegra: Add reserved-memory node for P3450 arm64: tegra: Enable NVDEC and NVENC on Tegra210 arm64: tegra: Fix APB DMA controller node name arm64: tegra: Add default GIC address cells on Tegra210 arm64: tegra: Add default GIC address cells on Tegra194 arm64: tegra: Add default GIC address cells on Tegra186 arm64: tegra: Add default GIC address cells on Tegra132 arm64: tegra: Add OPP tables on Tegra210 arm64: tegra: Add interconnect properties for Tegra210 arm64: tegra: Add ACTMON on Tegra210 arm64: tegra: Add device-tree node for NVVRS RTC arm64: tegra: Move avdd-dsi-csi-supply into CSI node arm64: tegra: Drop redundant clock and reset names from TSEC node arm64: tegra: Move HDA into the correct bus ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
252f83d547
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@ -3,6 +3,7 @@
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# Enables support for device-tree overlays
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DTC_FLAGS_tegra210-p2371-2180 := -@
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DTC_FLAGS_tegra210-p3450-0000 := -@
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DTC_FLAGS_tegra210-p3541-0000 := -@
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DTC_FLAGS_tegra186-p2771-0000 := -@
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DTC_FLAGS_tegra186-p3509-0000+p3636-0001 := -@
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DTC_FLAGS_tegra194-p2972-0000 := -@
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@ -19,6 +20,7 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3541-0000.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb
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dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
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@ -175,6 +175,7 @@ i2c-bus {
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gic: interrupt-controller@50041000 {
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compatible = "arm,cortex-a15-gic";
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x50041000 0x0 0x1000>,
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@ -271,7 +272,7 @@ gpio: gpio@6000d000 {
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interrupt-controller;
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};
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apbdma: dma@60020000 {
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apbdma: dma-controller@60020000 {
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compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
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reg = <0x0 0x60020000 0x0 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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@ -671,7 +671,6 @@ connector {
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vbus-gpios = <&gpio
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TEGRA186_MAIN_GPIO(L, 4)
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GPIO_ACTIVE_LOW>;
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id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
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};
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};
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@ -36,6 +36,12 @@ gpio: gpio@2200000 {
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interrupt-controller;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pinmux 0 0 140>;
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};
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pinmux: pinmux@2430000 {
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compatible = "nvidia,tegra186-pinmux";
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reg = <0x0 0x2430000 0x0 0x15000>;
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};
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ethernet@2490000 {
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@ -1173,6 +1179,7 @@ fuse@3820000 {
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gic: interrupt-controller@3881000 {
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compatible = "arm,gic-400";
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x03881000 0x0 0x1000>,
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@ -1274,10 +1281,16 @@ gpio_aon: gpio@c2f0000 {
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinmux_aon 0 0 47>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pinmux_aon: pinmux@c300000 {
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compatible = "nvidia,tegra186-pinmux-aon";
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reg = <0x0 0xc300000 0x0 0x4000>;
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};
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pwm4: pwm@c340000 {
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compatible = "nvidia,tegra186-pwm";
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reg = <0x0 0xc340000 0x0 0x10000>;
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@ -42,6 +42,7 @@ phy: ethernet-phy@0 {
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
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#phy-cells = <0>;
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wakeup-source;
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};
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};
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};
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@ -1331,6 +1331,7 @@ fuse@3820000 {
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gic: interrupt-controller@3881000 {
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compatible = "arm,gic-400";
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x03881000 0x0 0x1000>,
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@ -18,6 +18,12 @@ chosen {
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stdout-path = "serial0:115200n8";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x1 0x0>;
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@ -20,10 +20,10 @@ dpaux@54040000 {
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vi@54080000 {
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status = "okay";
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avdd-dsi-csi-supply = <&vdd_dsi_csi>;
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csi@838 {
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status = "okay";
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avdd-dsi-csi-supply = <&vdd_dsi_csi>;
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};
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};
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@ -22,6 +22,12 @@ chosen {
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stdout-path = "serial0:115200n8";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x1 0x0>;
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@ -64,10 +70,10 @@ dpaux@54040000 {
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vi@54080000 {
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status = "okay";
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avdd-dsi-csi-supply = <&vdd_sys_1v2>;
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csi@838 {
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status = "okay";
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avdd-dsi-csi-supply = <&vdd_sys_1v2>;
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};
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};
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@ -520,7 +526,7 @@ pcie-6 {
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ports {
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usb2-0 {
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status = "okay";
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mode = "peripheral";
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mode = "otg";
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usb-role-switch;
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vbus-supply = <&vdd_5v0_usb>;
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59
arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts
Normal file
59
arch/arm64/boot/dts/nvidia/tegra210-p3541-0000.dts
Normal file
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@ -0,0 +1,59 @@
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "tegra210-p3450-0000.dts"
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/ {
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model = "NVIDIA Jetson Nano 2GB Developer Kit";
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compatible = "nvidia,p3541-0000", "nvidia,p3450-0000", "nvidia,tegra210";
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memory@80000000 {
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reg = <0x0 0x80000000 0x0 0x80000000>;
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};
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host1x@50000000 {
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sor@54540000 {
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status = "disabled";
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};
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dpaux@545c0000 {
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status = "disabled";
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};
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};
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padctl@7009f000 {
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ports {
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usb2-1 {
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vbus-supply = <&vdd_hub_5v0>;
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};
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usb2-2 {
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vbus-supply = <&vdd_hub_5v0>;
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};
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usb3-0 {
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/delete-property/ vbus-supply;
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};
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};
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};
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regulator-vdd-hdmi-5v0 {
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gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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/delete-node/ regulator-vdd-hub-3v3;
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vdd_hub_5v0: regulator-vdd-hub-5v0 {
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compatible = "regulator-fixed";
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regulator-name = "VDD_HUB_5V0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <&vdd_5v0_sys>;
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};
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};
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135
arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi
Normal file
135
arch/arm64/boot/dts/nvidia/tegra210-peripherals-opp.dtsi
Normal file
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@ -0,0 +1,135 @@
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// SPDX-License-Identifier: GPL-2.0
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/ {
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/* EMC DVFS OPP table */
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emc_icc_dvfs_opp_table: opp-table-dvfs0 {
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compatible = "operating-points-v2";
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opp-40800000-800 {
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opp-microvolt = <800000 800000 1150000>;
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opp-hz = /bits/ 64 <40800000>;
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opp-supported-hw = <0x0003>;
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};
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opp-68000000-800 {
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opp-microvolt = <800000 800000 1150000>;
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opp-hz = /bits/ 64 <68000000>;
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opp-supported-hw = <0x0003>;
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};
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opp-102000000-800 {
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opp-microvolt = <800000 800000 1150000>;
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opp-hz = /bits/ 64 <102000000>;
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opp-supported-hw = <0x0003>;
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};
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opp-204000000-800 {
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opp-microvolt = <800000 800000 1150000>;
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opp-hz = /bits/ 64 <204000000>;
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opp-supported-hw = <0x0007>;
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opp-suspend;
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};
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opp-408000000-812 {
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opp-microvolt = <812000 812000 1150000>;
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opp-hz = /bits/ 64 <408000000>;
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opp-supported-hw = <0x0003>;
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};
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opp-665600000-825 {
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opp-microvolt = <825000 825000 1150000>;
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opp-hz = /bits/ 64 <665600000>;
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opp-supported-hw = <0x0003>;
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};
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opp-800000000-825 {
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opp-microvolt = <825000 825000 1150000>;
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opp-hz = /bits/ 64 <800000000>;
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opp-supported-hw = <0x0003>;
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};
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opp-1065600000-837 {
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opp-microvolt = <837000 837000 1150000>;
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opp-hz = /bits/ 64 <1065600000>;
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opp-supported-hw = <0x0003>;
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};
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opp-1331200000-850 {
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opp-microvolt = <850000 850000 1150000>;
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opp-hz = /bits/ 64 <1331200000>;
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opp-supported-hw = <0x0003>;
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};
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opp-1600000000-887 {
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opp-microvolt = <887000 887000 1150000>;
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opp-hz = /bits/ 64 <1600000000>;
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opp-supported-hw = <0x0007>;
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};
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};
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/* EMC bandwidth OPP table */
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emc_bw_dfs_opp_table: opp-table-dvfs1 {
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compatible = "operating-points-v2";
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opp-40800000 {
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opp-hz = /bits/ 64 <40800000>;
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opp-supported-hw = <0x0003>;
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opp-peak-kBps = <652800>;
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};
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opp-68000000 {
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opp-hz = /bits/ 64 <68000000>;
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opp-supported-hw = <0x0003>;
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opp-peak-kBps = <1088000>;
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};
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opp-102000000 {
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opp-hz = /bits/ 64 <102000000>;
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opp-supported-hw = <0x0003>;
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opp-peak-kBps = <1632000>;
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};
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opp-204000000 {
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opp-hz = /bits/ 64 <204000000>;
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opp-supported-hw = <0x0007>;
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opp-peak-kBps = <3264000>;
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opp-suspend;
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};
|
||||
|
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opp-408000000 {
|
||||
opp-hz = /bits/ 64 <408000000>;
|
||||
opp-supported-hw = <0x0003>;
|
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opp-peak-kBps = <6528000>;
|
||||
};
|
||||
|
||||
opp-665600000 {
|
||||
opp-hz = /bits/ 64 <665600000>;
|
||||
opp-supported-hw = <0x0003>;
|
||||
opp-peak-kBps = <10649600>;
|
||||
};
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-supported-hw = <0x001F>;
|
||||
opp-peak-kBps = <12800000>;
|
||||
};
|
||||
|
||||
opp-1065600000 {
|
||||
opp-hz = /bits/ 64 <1065600000>;
|
||||
opp-supported-hw = <0x0003>;
|
||||
opp-peak-kBps = <17049600>;
|
||||
};
|
||||
|
||||
opp-1331200000 {
|
||||
opp-hz = /bits/ 64 <1331200000>;
|
||||
opp-supported-hw = <0x0003>;
|
||||
opp-peak-kBps = <21299200>;
|
||||
};
|
||||
|
||||
opp-1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>;
|
||||
opp-supported-hw = <0x0007>;
|
||||
opp-peak-kBps = <25600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -9,6 +9,8 @@
|
|||
#include <dt-bindings/thermal/tegra124-soctherm.h>
|
||||
#include <dt-bindings/soc/tegra-pmc.h>
|
||||
|
||||
#include "tegra210-peripherals-opp.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "nvidia,tegra210";
|
||||
interrupt-parent = <&lic>;
|
||||
|
|
@ -183,9 +185,7 @@ tsec@54100000 {
|
|||
reg = <0x0 0x54100000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_TSEC>;
|
||||
clock-names = "tsec";
|
||||
resets = <&tegra_car 83>;
|
||||
reset-names = "tsec";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -202,6 +202,19 @@ dc@54200000 {
|
|||
|
||||
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
|
||||
nvidia,head = <0>;
|
||||
|
||||
interconnects = <&mc TEGRA210_MC_DISPLAY0A &emc>,
|
||||
<&mc TEGRA210_MC_DISPLAY0B &emc>,
|
||||
<&mc TEGRA210_MC_DISPLAY0C &emc>,
|
||||
<&mc TEGRA210_MC_DISPLAYHC &emc>,
|
||||
<&mc TEGRA210_MC_DISPLAYD &emc>,
|
||||
<&mc TEGRA210_MC_DISPLAYT &emc>;
|
||||
interconnect-names = "wina",
|
||||
"winb",
|
||||
"winc",
|
||||
"cursor",
|
||||
"wind",
|
||||
"wint";
|
||||
};
|
||||
|
||||
dc@54240000 {
|
||||
|
|
@ -217,6 +230,15 @@ dc@54240000 {
|
|||
|
||||
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
|
||||
nvidia,head = <1>;
|
||||
|
||||
interconnects = <&mc TEGRA210_MC_DISPLAY0AB &emc>,
|
||||
<&mc TEGRA210_MC_DISPLAY0BB &emc>,
|
||||
<&mc TEGRA210_MC_DISPLAY0CB &emc>,
|
||||
<&mc TEGRA210_MC_DISPLAYHCB &emc>;
|
||||
interconnect-names = "wina",
|
||||
"winb",
|
||||
"winc",
|
||||
"cursor";
|
||||
};
|
||||
|
||||
dsia: dsi@54300000 {
|
||||
|
|
@ -253,7 +275,13 @@ vic@54340000 {
|
|||
nvjpg@54380000 {
|
||||
compatible = "nvidia,tegra210-nvjpg";
|
||||
reg = <0x0 0x54380000 0x0 0x00040000>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car TEGRA210_CLK_NVJPG>;
|
||||
clock-names = "nvjpg";
|
||||
resets = <&tegra_car 195>;
|
||||
reset-names = "nvjpg";
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_NVJPG>;
|
||||
power-domains = <&pd_nvjpg>;
|
||||
};
|
||||
|
||||
dsib: dsi@54400000 {
|
||||
|
|
@ -277,13 +305,25 @@ dsib: dsi@54400000 {
|
|||
nvdec@54480000 {
|
||||
compatible = "nvidia,tegra210-nvdec";
|
||||
reg = <0x0 0x54480000 0x0 0x00040000>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car TEGRA210_CLK_NVDEC>;
|
||||
clock-names = "nvdec";
|
||||
resets = <&tegra_car 194>;
|
||||
reset-names = "nvdec";
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_NVDEC>;
|
||||
power-domains = <&pd_nvdec>;
|
||||
};
|
||||
|
||||
nvenc@544c0000 {
|
||||
compatible = "nvidia,tegra210-nvenc";
|
||||
reg = <0x0 0x544c0000 0x0 0x00040000>;
|
||||
status = "disabled";
|
||||
clocks = <&tegra_car TEGRA210_CLK_NVENC>;
|
||||
clock-names = "nvenc";
|
||||
resets = <&tegra_car 219>;
|
||||
reset-names = "nvenc";
|
||||
|
||||
iommus = <&mc TEGRA_SWGROUP_NVENC>;
|
||||
power-domains = <&pd_nvenc>;
|
||||
};
|
||||
|
||||
tsec@54500000 {
|
||||
|
|
@ -409,6 +449,7 @@ i2c@546c0000 {
|
|||
|
||||
gic: interrupt-controller@50041000 {
|
||||
compatible = "arm,gic-400";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x50041000 0x0 0x1000>,
|
||||
|
|
@ -485,6 +526,21 @@ flow-controller@60007000 {
|
|||
reg = <0x0 0x60007000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
actmon@6000c800 {
|
||||
compatible = "nvidia,tegra210-actmon", "nvidia,tegra124-actmon";
|
||||
reg = <0x0 0x6000c800 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_ACTMON>,
|
||||
<&tegra_car TEGRA210_CLK_EMC>;
|
||||
clock-names = "actmon", "emc";
|
||||
resets = <&tegra_car 119>;
|
||||
reset-names = "actmon";
|
||||
operating-points-v2 = <&emc_bw_dfs_opp_table>;
|
||||
interconnects = <&mc TEGRA210_MC_MPCORER &emc>;
|
||||
interconnect-names = "cpu-read";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
gpio: gpio@6000d000 {
|
||||
compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
|
||||
reg = <0x0 0x6000d000 0x0 0x1000>;
|
||||
|
|
@ -502,7 +558,7 @@ gpio: gpio@6000d000 {
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
apbdma: dma@60020000 {
|
||||
apbdma: dma-controller@60020000 {
|
||||
compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
|
||||
reg = <0x0 0x60020000 0x0 0x1400>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -894,6 +950,18 @@ pd_audio: aud {
|
|||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_nvenc: mpe {
|
||||
clocks = <&tegra_car TEGRA210_CLK_NVENC>;
|
||||
resets = <&tegra_car 219>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_nvdec: nvdec {
|
||||
clocks = <&tegra_car TEGRA210_CLK_NVDEC>;
|
||||
resets = <&tegra_car 194>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_sor: sor {
|
||||
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
|
||||
<&tegra_car TEGRA210_CLK_SOR1>,
|
||||
|
|
@ -947,6 +1015,12 @@ pd_xusbhost: xusbc {
|
|||
resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_nvjpg: nvjpg {
|
||||
clocks = <&tegra_car TEGRA210_CLK_NVJPG>;
|
||||
resets = <&tegra_car 195>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -978,6 +1052,7 @@ mc: memory-controller@70019000 {
|
|||
|
||||
#iommu-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
emc: external-memory-controller@7001b000 {
|
||||
|
|
@ -989,6 +1064,9 @@ emc: external-memory-controller@7001b000 {
|
|||
clock-names = "emc";
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
nvidia,memory-controller = <&mc>;
|
||||
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
|
||||
|
||||
#interconnect-cells = <0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ / {
|
|||
aliases {
|
||||
mmc0 = "/bus@0/mmc@3460000";
|
||||
mmc1 = "/bus@0/mmc@3400000";
|
||||
rtc0 = "/bpmp/i2c/pmic@3c";
|
||||
};
|
||||
|
||||
bus@0 {
|
||||
|
|
@ -170,6 +171,16 @@ bpmp {
|
|||
i2c {
|
||||
status = "okay";
|
||||
|
||||
pmic@3c {
|
||||
compatible = "nvidia,vrs-10";
|
||||
reg = <0x3c>;
|
||||
interrupt-parent = <&pmc>;
|
||||
/* VRS Wake ID is 24 */
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
thermal-sensor@4c {
|
||||
compatible = "ti,tmp451";
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ / {
|
|||
|
||||
aliases {
|
||||
mmc0 = "/bus@0/mmc@3400000";
|
||||
rtc0 = "/bpmp/i2c/pmic@3c";
|
||||
};
|
||||
|
||||
bus@0 {
|
||||
|
|
@ -121,6 +122,20 @@ pmc@c360000 {
|
|||
};
|
||||
};
|
||||
|
||||
bpmp {
|
||||
i2c {
|
||||
pmic@3c {
|
||||
compatible = "nvidia,vrs-10";
|
||||
reg = <0x3c>;
|
||||
interrupt-parent = <&pmc>;
|
||||
/* VRS Wake ID is 24 */
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_5v0_sys: regulator-vdd-5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_5V0_SYS";
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#include <dt-bindings/power/tegra234-powergate.h>
|
||||
#include <dt-bindings/reset/tegra234-reset.h>
|
||||
#include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
|
||||
/ {
|
||||
compatible = "nvidia,tegra234";
|
||||
|
|
@ -127,6 +128,56 @@ gpio: gpio@2200000 {
|
|||
pinmux: pinmux@2430000 {
|
||||
compatible = "nvidia,tegra234-pinmux";
|
||||
reg = <0x0 0x2430000 0x0 0x19100>;
|
||||
|
||||
pex_rst_c4_in_state: pinmux-pex-rst-c4-in {
|
||||
pex_rst {
|
||||
nvidia,pins = "pex_l4_rst_n_pl1";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
|
||||
pex_rst_c5_in_state: pinmux-pex-rst-c5-in {
|
||||
pex_rst {
|
||||
nvidia,pins = "pex_l5_rst_n_paf1";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
|
||||
pex_rst_c6_in_state: pinmux-pex-rst-c6-in {
|
||||
pex_rst {
|
||||
nvidia,pins = "pex_l6_rst_n_paf3";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
|
||||
pex_rst_c7_in_state: pinmux-pex-rst-c7-in {
|
||||
pex_rst {
|
||||
nvidia,pins = "pex_l7_rst_n_pag1";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
|
||||
pex_rst_c10_in_state: pinmux-pex-rst-c10-in {
|
||||
pex_rst {
|
||||
nvidia,pins = "pex_l10_rst_n_pag7";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpcdma: dma-controller@2600000 {
|
||||
|
|
@ -3276,8 +3327,15 @@ usb@3610000 {
|
|||
<0x0 0x03650000 0x0 0x10000>;
|
||||
reg-names = "hcd", "fpci", "bar2";
|
||||
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pmc 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pmc 77 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pmc 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pmc 79 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pmc 80 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pmc 81 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pmc 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
|
||||
<&bpmp TEGRA234_CLK_XUSB_FALCON>,
|
||||
|
|
@ -4630,6 +4688,8 @@ pcie-ep@140e0000 {
|
|||
<&bpmp TEGRA234_RESET_PEX2_CORE_10>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pex_rst_c10_in_state>;
|
||||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
|
|
@ -4881,6 +4941,8 @@ pcie-ep@14160000 {
|
|||
<&bpmp TEGRA234_RESET_PEX0_CORE_4>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pex_rst_c4_in_state>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
nvidia,bpmp = <&bpmp 4>;
|
||||
|
|
@ -5023,6 +5085,8 @@ pcie-ep@141a0000 {
|
|||
<&bpmp TEGRA234_RESET_PEX1_CORE_5>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pex_rst_c5_in_state>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
|
|
@ -5115,6 +5179,8 @@ pcie-ep@141c0000 {
|
|||
<&bpmp TEGRA234_RESET_PEX1_CORE_6>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pex_rst_c6_in_state>;
|
||||
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
|
|
@ -5207,6 +5273,8 @@ pcie-ep@141e0000 {
|
|||
<&bpmp TEGRA234_RESET_PEX2_CORE_7>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pex_rst_c7_in_state>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,112 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
|
||||
/ {
|
||||
bus@0 {
|
||||
aconnect@9000000 {
|
||||
status = "okay";
|
||||
|
||||
dma-controller@9440000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ahub@9630000 {
|
||||
status = "okay";
|
||||
|
||||
i2s@9280000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2s@9290000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2s@92b0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
interrupt-controller@9960000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
bus@8800000000 {
|
||||
hda@90b0000 {
|
||||
nvidia,model = "NVIDIA Jetson Thor AGX HDA";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
status = "okay";
|
||||
|
||||
dais = /* ADMAIF (FE) Ports */
|
||||
<&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
|
||||
<&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
|
||||
<&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
|
||||
<&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
|
||||
<&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
|
||||
<&admaif20_port>, <&admaif21_port>, <&admaif22_port>, <&admaif23_port>,
|
||||
<&admaif24_port>, <&admaif25_port>, <&admaif26_port>, <&admaif27_port>,
|
||||
<&admaif28_port>, <&admaif29_port>, <&admaif30_port>, <&admaif31_port>,
|
||||
/* XBAR Ports */
|
||||
<&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
|
||||
<&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
|
||||
<&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
|
||||
<&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
|
||||
<&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
|
||||
<&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
|
||||
<&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
|
||||
<&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
|
||||
<&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
|
||||
<&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
|
||||
<&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
|
||||
<&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
|
||||
<&xbar_amx5_in1_port>, <&xbar_amx5_in2_port>,
|
||||
<&xbar_amx5_in3_port>, <&xbar_amx5_in4_port>,
|
||||
<&xbar_amx6_in1_port>, <&xbar_amx6_in2_port>,
|
||||
<&xbar_amx6_in3_port>, <&xbar_amx6_in4_port>,
|
||||
<&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
|
||||
<&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
|
||||
<&xbar_adx5_in_port>, <&xbar_adx6_in_port>,
|
||||
<&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
|
||||
<&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
|
||||
<&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
|
||||
<&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
|
||||
<&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
|
||||
<&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
|
||||
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
|
||||
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
|
||||
<&xbar_asrc_in7_port>,
|
||||
<&xbar_ope1_in_port>,
|
||||
/* HW accelerators */
|
||||
<&sfc1_out_port>, <&sfc2_out_port>,
|
||||
<&sfc3_out_port>, <&sfc4_out_port>,
|
||||
<&mvc1_out_port>, <&mvc2_out_port>,
|
||||
<&amx1_out_port>, <&amx2_out_port>,
|
||||
<&amx3_out_port>, <&amx4_out_port>,
|
||||
<&amx5_out_port>, <&amx6_out_port>,
|
||||
<&adx1_out1_port>, <&adx1_out2_port>,
|
||||
<&adx1_out3_port>, <&adx1_out4_port>,
|
||||
<&adx2_out1_port>, <&adx2_out2_port>,
|
||||
<&adx2_out3_port>, <&adx2_out4_port>,
|
||||
<&adx3_out1_port>, <&adx3_out2_port>,
|
||||
<&adx3_out3_port>, <&adx3_out4_port>,
|
||||
<&adx4_out1_port>, <&adx4_out2_port>,
|
||||
<&adx4_out3_port>, <&adx4_out4_port>,
|
||||
<&adx5_out1_port>, <&adx5_out2_port>,
|
||||
<&adx5_out3_port>, <&adx5_out4_port>,
|
||||
<&adx6_out1_port>, <&adx6_out2_port>,
|
||||
<&adx6_out3_port>, <&adx6_out4_port>,
|
||||
<&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
|
||||
<&mix_out4_port>, <&mix_out5_port>,
|
||||
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
|
||||
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
|
||||
<&ope1_out_port>,
|
||||
/* BE I/O Ports */
|
||||
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>;
|
||||
|
||||
label = "NVIDIA Jetson Thor AGX APE";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user