mirror of
https://github.com/torvalds/linux.git
synced 2026-05-25 23:52:08 +02:00
Amlogic ARM64 DT changes for v6.10:
- New Boards: - MNT Reform 2 CM4 adapter with a BPI-CM4 Module - AV400 (Amlogic A5) - BA400 (Amlogic A4) - Initial Amlogic A4 & A5 support - MIPI DSI support for G12A, G12B & SM1 SoCs - Overlay for Khadas TS050 panel for the Khadas VIM3/VIM3L - Amlogic T7 reset controller -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmY0oH4ACgkQd9zb2sjI SdEHJQ/+PvjlKb/+tCYk4/zNEu1AsKjWOlzF5dxT0uSCr+FsqMf9d58EwmqfUmgI OHAPq3ju+pjU0BHBqjmDcW9ksLdY+D7wY+qbqz+ROlvYD6P0NgZizasRYesMnMI0 D2X3WQINq2rJABUswC4uAnqLAGvlXSM+X2nsEtFW792zfZyOsnB6Lr3DfyGAOqqU rDaUdmBNy8mQ37X5FvE9t34Wv1Ds5815n+JkOj8QXv+F7cn03rDZrz5Wxhf2BuNc MSIPlfc0F+aRMMu1FAZ7m63f+Y/SyTBwC25+At408y4jlPhp0S9ktj1FMF8OcVrF E73x2fGKYgfSD4W7K0iG+hjO+i+vyid+852T6H5V6x040mlJG5QKW/yDJoFJerh7 eX0zMr4F1HNwaypnQYNfIeGAmdUNIeUvBb5f+2jk3t/jindxB9TCpLXl5SNugCfR vuwk/slJlwdhPcElvWeAvOc7DBpXBDUsfBjhQ24Lt/DDQvHunardBYmGjDzRBWKX kLf3D6EgdrOpMoyioeh2aZdTiFH9xRyTuHIHZrm6Gevu5XcU8Zw4GQ8eboUM6GtH bQUcw1SN5G0/HmOzRcXTmggbCggvwMnof0XhdxU6K/jTJnE0Ywus/9AtcYBJsL7j 0g8T8bzs6uLB7FwTFdbliE8uQFxauQFXm9qQ5GXIagMXvirqkDk= =BAJ1 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmY59RMACgkQYKtH/8kJ UifZXxAA20iI+MkJULdk0WFp+9pk6Kiym5K2PmL1KQGkYHORRs4PjvauqUD1OlYA 4KmHculOZnsaQMuGWLxMacQ33GLRN3Bf0+T0pVk8SBENRKb5102TaYpf4dL9PwLl gX1g6r7q7BgZNIspwld3TbMAsLGqNtBxPIuzQ4VG9xFc0ezCGyXJmWecp69uSiuK 9/RB4CbYeuqn6mSyXDxQVXnDsyDEGaqhD8xZRagaG6oDVp9jyQjDp1UlihsO9GI0 Qmv3kYEp/pHWj8AVNEcFJ/3VBQEzinPjhscdTeDp9f5nF/VG3OeSMg1t0oQ/P9TS DpiWBxAlr1195gpqQM2n49f0nCiw/epsxaMaohIIlELEnIpIfzTAEMTOcrsNDK/l esXRm05Leh9Mu3CSR6ESiIbFHK2BhQ0DGTQflaf4zrsm8xvd/fbMfFU3Y9cFFbRH COks1T54SKUqLiawWZ6v8WOACjLW/8OceVbuo1GUerThyVlWeVf6EbH4t9MSIekg hNbmy02tDtKf2t5amhOgyaVcu9RLzTh13ilEL/i7Q9+81FH03iv41xJbvmnIqIoP Bk5hD2Ci3A2x9SinFX6t5ycVaSyPKNQnwacx8BSkALC9iCIqbYTZJT6s+3D0LfZo 350aL9xLEkDLSZ2sz6oMhJdS7iG261HHyF3fJ75aX9jYAfUjFl8= =wiuz -----END PGP SIGNATURE----- Merge tag 'amlogic-arm64-dt-for-v6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt-late Amlogic ARM64 DT changes for v6.10: - New Boards: - MNT Reform 2 CM4 adapter with a BPI-CM4 Module - AV400 (Amlogic A5) - BA400 (Amlogic A4) - Initial Amlogic A4 & A5 support - MIPI DSI support for G12A, G12B & SM1 SoCs - Overlay for Khadas TS050 panel for the Khadas VIM3/VIM3L - Amlogic T7 reset controller * tag 'amlogic-arm64-dt-for-v6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: arm64: dts: amlogic: Add Amlogic T7 reset controller arm64: dts: add support for A5 based Amlogic AV400 arm64: dts: add support for A4 based Amlogic BA400 dt-bindings: serial: amlogic,meson-uart: Add compatible string for A4 dt-bindings: arm: amlogic: add A5 support dt-bindings: arm: amlogic: add A4 support arm64: dts: meson: fix S4 power-controller node arm64: dts: amlogic: meson-g12b-bananapi-cm4: add support for MNT Reform2 with CM4 adaper arm64: meson: khadas-vim3l: add TS050 DSI panel overlay arm64: meson: g12-common: add the MIPI DSI nodes dt-bindings: arm: amlogic: Document the MNT Reform 2 CM4 adapter with a BPI-CM4 Module Link: https://lore.kernel.org/r/6030a450-fb4e-4e27-a5c3-6f4e0f326d9a@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
24ae5d2489
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@ -157,6 +157,7 @@ properties:
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items:
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- enum:
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- bananapi,bpi-cm4io
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- mntre,reform2-cm4
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- const: bananapi,bpi-cm4
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- const: amlogic,a311d
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- const: amlogic,g12b
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@ -201,6 +202,18 @@ properties:
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- amlogic,ad402
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- const: amlogic,a1
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- description: Boards with the Amlogic A4 A113L2 SoC
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items:
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- enum:
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- amlogic,ba400
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- const: amlogic,a4
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- description: Boards with the Amlogic A5 A113X2 SoC
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items:
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- enum:
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- amlogic,av400
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- const: amlogic,a5
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- description: Boards with the Amlogic C3 C302X/C308L SoC
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items:
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- enum:
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@ -54,7 +54,9 @@ properties:
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- const: amlogic,meson-gx-uart
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- description: UART controller on S4 compatible SoCs
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items:
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- const: amlogic,t7-uart
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- enum:
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- amlogic,a4-uart
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- amlogic,t7-uart
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- const: amlogic,meson-s4-uart
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reg:
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@ -1,4 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-a5-a113x2-av400.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
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@ -16,7 +18,9 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-bananapi-m2s.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3-ts050.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-cm4io.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-mnt-reform2.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb
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@ -76,6 +80,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m2-pro.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l-ts050.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-sm1-s905d3-libretech-cc.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb
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@ -86,3 +91,5 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb
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# Overlays
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meson-g12a-fbx8am-brcm-dtbs := meson-g12a-fbx8am.dtb meson-g12a-fbx8am-brcm.dtbo
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meson-g12a-fbx8am-realtek-dtbs := meson-g12a-fbx8am.dtb meson-g12a-fbx8am-realtek.dtbo
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meson-g12b-a311d-khadas-vim3-ts050-dtbs := meson-g12b-a311d-khadas-vim3.dtb meson-khadas-vim3-ts050.dtbo
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meson-sm1-khadas-vim3l-ts050-dtbs := meson-sm1-khadas-vim3l.dtb meson-khadas-vim3-ts050.dtbo
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42
arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
Normal file
42
arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
Normal file
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@ -0,0 +1,42 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "amlogic-a4.dtsi"
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/ {
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model = "Amlogic A113L2 ba400 Development Board";
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compatible = "amlogic,ba400", "amlogic,a4";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart_b;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 10 MiB reserved for ARM Trusted Firmware */
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secmon_reserved: secmon@5000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x05000000 0x0 0xa00000>;
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no-map;
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};
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};
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};
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&uart_b {
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status = "okay";
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};
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66
arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi
Normal file
66
arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi
Normal file
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@ -0,0 +1,66 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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xtal: xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@fff01000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xfff01000 0 0x1000>,
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<0x0 0xfff02000 0 0x2000>,
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<0x0 0xfff04000 0 0x2000>,
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<0x0 0xfff06000 0 0x2000>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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apb: bus@fe000000 {
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compatible = "simple-bus";
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reg = <0x0 0xfe000000 0x0 0x480000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
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uart_b: serial@7a000 {
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compatible = "amlogic,a4-uart",
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"amlogic,meson-s4-uart";
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reg = <0x0 0x7a000 0x0 0x18>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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};
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};
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};
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40
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
Normal file
40
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
Normal file
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@ -0,0 +1,40 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
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*/
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#include "amlogic-a4-common.dtsi"
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/ {
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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};
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};
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42
arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts
Normal file
42
arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts
Normal file
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@ -0,0 +1,42 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "amlogic-a5.dtsi"
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/ {
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model = "Amlogic A113X2 av400 Development Board";
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compatible = "amlogic,av400", "amlogic,a5";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart_b;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 10 MiB reserved for ARM Trusted Firmware */
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secmon_reserved: secmon@5000000 {
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compatible = "shared-dma-pool";
|
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reg = <0x0 0x05000000 0x0 0xa00000>;
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no-map;
|
||||
};
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||||
};
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||||
};
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|
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&uart_b {
|
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status = "okay";
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||||
};
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40
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
Normal file
40
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "amlogic-a4-common.dtsi"
|
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/ {
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
};
|
||||
197
arch/arm64/boot/dts/amlogic/amlogic-t7-reset.h
Normal file
197
arch/arm64/boot/dts/amlogic/amlogic-t7-reset.h
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DTS_AMLOGIC_T7_RESET_H
|
||||
#define __DTS_AMLOGIC_T7_RESET_H
|
||||
|
||||
/* RESET0 */
|
||||
/* 0-3 */
|
||||
#define RESET_USB 4
|
||||
#define RESET_U2DRD 5
|
||||
#define RESET_U3DRD 6
|
||||
#define RESET_U3DRD_PIPE0 7
|
||||
#define RESET_U2PHY20 8
|
||||
#define RESET_U2PHY21 9
|
||||
#define RESET_GDC 10
|
||||
#define RESET_HDMI20_AES 11
|
||||
#define RESET_HDMIRX 12
|
||||
#define RESET_HDMIRX_APB 13
|
||||
#define RESET_DEWARP 14
|
||||
/* 15 */
|
||||
#define RESET_HDMITX_CAPB3 16
|
||||
#define RESET_BRG_VCBUG_DEC 17
|
||||
#define RESET_VCBUS 18
|
||||
#define RESET_VID_PLL_DIV 19
|
||||
#define RESET_VDI6 20
|
||||
#define RESET_GE2D 21
|
||||
#define RESET_HDMITXPHY 22
|
||||
#define RESET_VID_LOCK 23
|
||||
#define RESET_VENC0 24
|
||||
#define RESET_VDAC 25
|
||||
#define RESET_VENC2 26
|
||||
#define RESET_VENC1 27
|
||||
#define RESET_RDMA 28
|
||||
#define RESET_HDMITX 29
|
||||
#define RESET_VIU 30
|
||||
#define RESET_VENC 31
|
||||
|
||||
/* RESET1 */
|
||||
#define RESET_AUDIO 32
|
||||
#define RESET_MALI_CAPB3 33
|
||||
#define RESET_MALI 34
|
||||
#define RESET_DDR_APB 35
|
||||
#define RESET_DDR 36
|
||||
#define RESET_DOS_CAPB3 37
|
||||
#define RESET_DOS 38
|
||||
#define RESET_COMBO_DPHY_CHAN2 39
|
||||
#define RESET_DEBUG_B 40
|
||||
#define RESET_DEBUG_A 41
|
||||
#define RESET_DSP_B 42
|
||||
#define RESET_DSP_A 43
|
||||
#define RESET_PCIE_A 44
|
||||
#define RESET_PCIE_PHY 45
|
||||
#define RESET_PCIE_APB 46
|
||||
#define RESET_ANAKIN 47
|
||||
#define RESET_ETH 48
|
||||
#define RESET_EDP0_CTRL 49
|
||||
#define RESET_EDP1_CTRL 50
|
||||
#define RESET_COMBO_DPHY_CHAN0 51
|
||||
#define RESET_COMBO_DPHY_CHAN1 52
|
||||
#define RESET_DSI_LVDS_EDP_TOP 53
|
||||
#define RESET_PCIE1_PHY 54
|
||||
#define RESET_PCIE1_APB 55
|
||||
#define RESET_DDR_1 56
|
||||
/* 57 */
|
||||
#define RESET_EDP1_PIPELINE 58
|
||||
#define RESET_EDP0_PIPELINE 59
|
||||
#define RESET_MIPI_DSI1_PHY 60
|
||||
#define RESET_MIPI_DSI0_PHY 61
|
||||
#define RESET_MIPI_DSI_A_HOST 62
|
||||
#define RESET_MIPI_DSI_B_HOST 63
|
||||
|
||||
/* RESET2 */
|
||||
#define RESET_DEVICE_MMC_ARB 64
|
||||
#define RESET_IR_CTRL 65
|
||||
#define RESET_TS_A73 66
|
||||
#define RESET_TS_A53 67
|
||||
#define RESET_SPICC_2 68
|
||||
#define RESET_SPICC_3 69
|
||||
#define RESET_SPICC_4 70
|
||||
#define RESET_SPICC_5 71
|
||||
#define RESET_SMART_CARD 72
|
||||
#define RESET_SPICC_0 73
|
||||
#define RESET_SPICC_1 74
|
||||
#define RESET_RSA 75
|
||||
/* 76-79 */
|
||||
#define RESET_MSR_CLK 80
|
||||
#define RESET_SPIFC 81
|
||||
#define RESET_SAR_ADC 82
|
||||
#define RESET_BT 83
|
||||
/* 84-87 */
|
||||
#define RESET_ACODEC 88
|
||||
#define RESET_CEC 89
|
||||
#define RESET_AFIFO 90
|
||||
#define RESET_WATCHDOG 91
|
||||
/* 92-95 */
|
||||
|
||||
/* RESET3 */
|
||||
#define RESET_BRG_NIC1_GPV 96
|
||||
#define RESET_BRG_NIC2_GPV 97
|
||||
#define RESET_BRG_NIC3_GPV 98
|
||||
#define RESET_BRG_NIC4_GPV 99
|
||||
#define RESET_BRG_NIC5_GPV 100
|
||||
/* 101-121 */
|
||||
#define RESET_MIPI_ISP 122
|
||||
#define RESET_BRG_ADB_MALI_1 123
|
||||
#define RESET_BRG_ADB_MALI_0 124
|
||||
#define RESET_BRG_ADB_A73 125
|
||||
#define RESET_BRG_ADB_A53 126
|
||||
#define RESET_BRG_CCI 127
|
||||
|
||||
/* RESET4 */
|
||||
#define RESET_PWM_AO_AB 128
|
||||
#define RESET_PWM_AO_CD 129
|
||||
#define RESET_PWM_AO_EF 130
|
||||
#define RESET_PWM_AO_GH 131
|
||||
#define RESET_PWM_AB 132
|
||||
#define RESET_PWM_CD 133
|
||||
#define RESET_PWM_EF 134
|
||||
/* 135-137 */
|
||||
#define RESET_UART_A 138
|
||||
#define RESET_UART_B 139
|
||||
#define RESET_UART_C 140
|
||||
#define RESET_UART_D 141
|
||||
#define RESET_UART_E 142
|
||||
#define RESET_UART_F 143
|
||||
#define RESET_I2C_S_A 144
|
||||
#define RESET_I2C_M_A 145
|
||||
#define RESET_I2C_M_B 146
|
||||
#define RESET_I2C_M_C 147
|
||||
#define RESET_I2C_M_D 148
|
||||
#define RESET_I2C_M_E 149
|
||||
#define RESET_I2C_M_F 150
|
||||
#define RESET_I2C_M_AO_A 151
|
||||
#define RESET_SD_EMMC_A 152
|
||||
#define RESET_SD_EMMC_B 153
|
||||
#define RESET_SD_EMMC_C 154
|
||||
#define RESET_I2C_M_AO_B 155
|
||||
#define RESET_TS_GPU 156
|
||||
#define RESET_TS_NNA 157
|
||||
#define RESET_TS_VPN 158
|
||||
#define RESET_TS_HEVC 159
|
||||
|
||||
/* RESET5 */
|
||||
#define RESET_BRG_NOC_DDR_1 160
|
||||
#define RESET_BRG_NOC_DDR_0 161
|
||||
#define RESET_BRG_NOC_MAIN 162
|
||||
#define RESET_BRG_NOC_ALL 163
|
||||
/* 164-167 */
|
||||
#define RESET_BRG_NIC2_SYS 168
|
||||
#define RESET_BRG_NIC2_MAIN 169
|
||||
#define RESET_BRG_NIC2_HDMI 170
|
||||
#define RESET_BRG_NIC2_ALL 171
|
||||
#define RESET_BRG_NIC3_WAVE 172
|
||||
#define RESET_BRG_NIC3_VDEC 173
|
||||
#define RESET_BRG_NIC3_HEVCF 174
|
||||
#define RESET_BRG_NIC3_HEVCB 175
|
||||
#define RESET_BRG_NIC3_HCODEC 176
|
||||
#define RESET_BRG_NIC3_GE2D 177
|
||||
#define RESET_BRG_NIC3_GDC 178
|
||||
#define RESET_BRG_NIC3_AMLOGIC 179
|
||||
#define RESET_BRG_NIC3_MAIN 180
|
||||
#define RESET_BRG_NIC3_ALL 181
|
||||
#define RESET_BRG_NIC5_VPU 182
|
||||
/* 183-185 */
|
||||
#define RESET_BRG_NIC4_DSPB 186
|
||||
#define RESET_BRG_NIC4_DSPA 187
|
||||
#define RESET_BRG_NIC4_VAPB 188
|
||||
#define RESET_BRG_NIC4_CLK81 189
|
||||
#define RESET_BRG_NIC4_MAIN 190
|
||||
#define RESET_BRG_NIC4_ALL 191
|
||||
|
||||
/* RESET6 */
|
||||
#define RESET_BRG_VDEC_PIPEL 192
|
||||
#define RESET_BRG_HEVCF_DMC_PIPEL 193
|
||||
#define RESET_BRG_NIC2TONIC4_PIPEL 194
|
||||
#define RESET_BRG_HDMIRXTONIC2_PIPEL 195
|
||||
#define RESET_BRG_SECTONIC4_PIPEL 196
|
||||
#define RESET_BRG_VPUTONOC_PIPEL 197
|
||||
#define RESET_BRG_NIC4TONOC_PIPEL 198
|
||||
#define RESET_BRG_NIC3TONOC_PIPEL 199
|
||||
#define RESET_BRG_NIC2TONOC_PIPEL 200
|
||||
#define RESET_BRG_NNATONOC_PIPEL 201
|
||||
#define RESET_BRG_FRISP3_PIPEL 202
|
||||
#define RESET_BRG_FRISP2_PIPEL 203
|
||||
#define RESET_BRG_FRISP1_PIPEL 204
|
||||
#define RESET_BRG_FRISP0_PIPEL 205
|
||||
/* 206-217 */
|
||||
#define RESET_BRG_AMPIPE_NAND 218
|
||||
#define RESET_BRG_AMPIPE_ETH 219
|
||||
/* 220 */
|
||||
#define RESET_BRG_AM2AXI0 221
|
||||
#define RESET_BRG_AM2AXI1 222
|
||||
#define RESET_BRG_AM2AXI2 223
|
||||
|
||||
#endif /* ___DTS_AMLOGIC_T7_RESET_H */
|
||||
|
|
@ -5,6 +5,7 @@
|
|||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/amlogic,t7-pwrc.h>
|
||||
#include "amlogic-t7-reset.h"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -149,6 +150,12 @@ apb4: bus@fe000000 {
|
|||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
|
||||
|
||||
reset: reset-controller@2000 {
|
||||
compatible = "amlogic,t7-reset";
|
||||
reg = <0x0 0x2000 0x0 0x98>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
watchdog@2100 {
|
||||
compatible = "amlogic,t7-wdt";
|
||||
reg = <0x0 0x2100 0x0 0x10>;
|
||||
|
|
|
|||
|
|
@ -1663,9 +1663,28 @@ pwrc: power-controller {
|
|||
<250000000>,
|
||||
<0>; /* Do Nothing */
|
||||
};
|
||||
|
||||
mipi_analog_dphy: phy {
|
||||
compatible = "amlogic,g12a-mipi-dphy-analog";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mipi_dphy: phy@44000 {
|
||||
compatible = "amlogic,axg-mipi-dphy";
|
||||
reg = <0x0 0x44000 0x0 0x2000>;
|
||||
clocks = <&clkc CLKID_MIPI_DSI_PHY>;
|
||||
clock-names = "pclk";
|
||||
resets = <&reset RESET_MIPI_DSI_PHY>;
|
||||
reset-names = "phy";
|
||||
phys = <&mipi_analog_dphy>;
|
||||
phy-names = "analog";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3_pcie_phy: phy@46000 {
|
||||
compatible = "amlogic,g12a-usb3-pcie-phy";
|
||||
reg = <0x0 0x46000 0x0 0x2000>;
|
||||
|
|
@ -2152,6 +2171,15 @@ hdmi_tx_out: endpoint {
|
|||
remote-endpoint = <&hdmi_tx_in>;
|
||||
};
|
||||
};
|
||||
|
||||
/* DPI output port */
|
||||
dpi_port: port@2 {
|
||||
reg = <2>;
|
||||
|
||||
dpi_out: endpoint {
|
||||
remote-endpoint = <&mipi_dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ffc01000 {
|
||||
|
|
@ -2189,6 +2217,48 @@ gpio_intc: interrupt-controller@f080 {
|
|||
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
|
||||
};
|
||||
|
||||
mipi_dsi: dsi@7000 {
|
||||
compatible = "amlogic,meson-g12a-dw-mipi-dsi";
|
||||
reg = <0x0 0x7000 0x0 0x1000>;
|
||||
resets = <&reset RESET_MIPI_DSI_HOST>;
|
||||
reset-names = "top";
|
||||
clocks = <&clkc CLKID_MIPI_DSI_HOST>,
|
||||
<&clkc CLKID_MIPI_DSI_PXCLK>,
|
||||
<&clkc CLKID_CTS_ENCL>;
|
||||
clock-names = "pclk", "bit", "px";
|
||||
phys = <&mipi_dphy>;
|
||||
phy-names = "dphy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
assigned-clocks = <&clkc CLKID_MIPI_DSI_PXCLK_SEL>,
|
||||
<&clkc CLKID_CTS_ENCL_SEL>,
|
||||
<&clkc CLKID_VCLK2_SEL>;
|
||||
assigned-clock-parents = <&clkc CLKID_GP0_PLL>,
|
||||
<&clkc CLKID_VCLK2_DIV1>,
|
||||
<&clkc CLKID_GP0_PLL>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* VPU VENC Input */
|
||||
mipi_dsi_venc_port: port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mipi_dsi_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
/* DSI Output */
|
||||
mipi_dsi_panel_port: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
watchdog: watchdog@f0d0 {
|
||||
compatible = "amlogic,meson-gxbb-wdt";
|
||||
reg = <0x0 0xf0d0 0x0 0x10>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,384 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
|
||||
* Copyright 2023 MNT Research GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-g12b-bananapi-cm4.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
|
||||
|
||||
/ {
|
||||
model = "MNT Reform 2 with BPI-CM4 Module";
|
||||
compatible = "mntre,reform2-cm4", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";
|
||||
chassis-type = "laptop";
|
||||
|
||||
aliases {
|
||||
ethernet0 = ðmac;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c3;
|
||||
};
|
||||
|
||||
hdmi_connector: hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-blue {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led-green {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "amlogic,axg-sound-card";
|
||||
model = "MNT-REFORM2-BPI-CM4";
|
||||
audio-widgets = "Headphone", "Headphone Jack",
|
||||
"Speaker", "External Speaker",
|
||||
"Microphone", "Mic Jack";
|
||||
audio-aux-devs = <&tdmout_a>, <&tdmout_b>, <&tdmin_b>;
|
||||
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
|
||||
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
|
||||
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
|
||||
"TDM_A Playback", "TDMOUT_A OUT",
|
||||
"TDMOUT_B IN 0", "FRDDR_A OUT 1",
|
||||
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
|
||||
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
|
||||
"TDM_B Playback", "TDMOUT_B OUT",
|
||||
"TDMIN_B IN 1", "TDM_B Capture",
|
||||
"TDMIN_B IN 4", "TDM_B Loopback",
|
||||
"TODDR_A IN 1", "TDMIN_B OUT",
|
||||
"TODDR_B IN 1", "TDMIN_B OUT",
|
||||
"TODDR_C IN 1", "TDMIN_B OUT",
|
||||
"Headphone Jack", "HP_L",
|
||||
"Headphone Jack", "HP_R",
|
||||
"External Speaker", "SPK_LP",
|
||||
"External Speaker", "SPK_LN",
|
||||
"External Speaker", "SPK_RP",
|
||||
"External Speaker", "SPK_RN",
|
||||
"LINPUT1", "Mic Jack",
|
||||
"Mic Jack", "MICB";
|
||||
|
||||
assigned-clocks = <&clkc CLKID_MPLL2>,
|
||||
<&clkc CLKID_MPLL0>,
|
||||
<&clkc CLKID_MPLL1>;
|
||||
assigned-clock-parents = <0>, <0>, <0>;
|
||||
assigned-clock-rates = <294912000>,
|
||||
<270950400>,
|
||||
<393216000>;
|
||||
|
||||
dai-link-0 {
|
||||
sound-dai = <&frddr_a>;
|
||||
};
|
||||
|
||||
dai-link-1 {
|
||||
sound-dai = <&frddr_b>;
|
||||
};
|
||||
|
||||
dai-link-2 {
|
||||
sound-dai = <&frddr_c>;
|
||||
};
|
||||
|
||||
dai-link-3 {
|
||||
sound-dai = <&toddr_a>;
|
||||
};
|
||||
|
||||
dai-link-4 {
|
||||
sound-dai = <&toddr_b>;
|
||||
};
|
||||
|
||||
dai-link-5 {
|
||||
sound-dai = <&toddr_c>;
|
||||
};
|
||||
|
||||
/* 8ch hdmi interface */
|
||||
dai-link-6 {
|
||||
sound-dai = <&tdmif_a>;
|
||||
dai-format = "i2s";
|
||||
dai-tdm-slot-tx-mask-0 = <1 1>;
|
||||
dai-tdm-slot-tx-mask-1 = <1 1>;
|
||||
dai-tdm-slot-tx-mask-2 = <1 1>;
|
||||
dai-tdm-slot-tx-mask-3 = <1 1>;
|
||||
mclk-fs = <256>;
|
||||
|
||||
codec {
|
||||
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Analog Audio */
|
||||
dai-link-7 {
|
||||
sound-dai = <&tdmif_b>;
|
||||
dai-format = "i2s";
|
||||
dai-tdm-slot-tx-mask-0 = <1 1>;
|
||||
mclk-fs = <256>;
|
||||
|
||||
codec {
|
||||
sound-dai = <&wm8960>;
|
||||
};
|
||||
};
|
||||
|
||||
/* hdmi glue */
|
||||
dai-link-8 {
|
||||
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
|
||||
|
||||
codec {
|
||||
sound-dai = <&hdmi_tx>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reg_main_1v8: regulator-main-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <®_main_3v3>;
|
||||
};
|
||||
|
||||
reg_main_1v2: regulator-main-1v2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1V2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
vin-supply = <®_main_5v>;
|
||||
};
|
||||
|
||||
reg_main_3v3: regulator-main-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_main_5v: regulator-main-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_main_usb: regulator-main-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB_PWR";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <®_main_5v>;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm_AO_ab 0 10000 0>;
|
||||
power-supply = <®_main_usb>;
|
||||
enable-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>;
|
||||
brightness-levels = <0 32 64 128 160 200 255>;
|
||||
default-brightness-level = <6>;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "innolux,n125hce-gn1";
|
||||
power-supply = <®_main_3v3>;
|
||||
backlight = <&backlight>;
|
||||
no-hpd;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&edp_bridge_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clock_12288: clock_12288 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_analog_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi_dsi {
|
||||
status = "okay";
|
||||
|
||||
assigned-clocks = <&clkc CLKID_GP0_PLL>,
|
||||
<&clkc CLKID_MIPI_DSI_PXCLK_SEL>,
|
||||
<&clkc CLKID_MIPI_DSI_PXCLK>,
|
||||
<&clkc CLKID_CTS_ENCL_SEL>,
|
||||
<&clkc CLKID_VCLK2_SEL>;
|
||||
assigned-clock-parents = <0>,
|
||||
<&clkc CLKID_GP0_PLL>,
|
||||
<0>,
|
||||
<&clkc CLKID_VCLK2_DIV1>,
|
||||
<&clkc CLKID_GP0_PLL>;
|
||||
assigned-clock-rates = <936000000>,
|
||||
<0>,
|
||||
<936000000>,
|
||||
<0>,
|
||||
<0>;
|
||||
};
|
||||
|
||||
&mipi_dsi_panel_port {
|
||||
mipi_dsi_out: endpoint {
|
||||
remote-endpoint = <&edp_bridge_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&cecb_AO {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_tx_tmds_port {
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm_AO_ab {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_ao_a_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
edp_bridge: bridge@2c {
|
||||
compatible = "ti,sn65dsi86";
|
||||
reg = <0x2c>;
|
||||
enable-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_HIGH>; // PIN_24 / GPIO8
|
||||
vccio-supply = <®_main_1v8>;
|
||||
vpll-supply = <®_main_1v8>;
|
||||
vcca-supply = <®_main_1v2>;
|
||||
vcc-supply = <®_main_1v2>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
edp_bridge_in: endpoint {
|
||||
remote-endpoint = <&mipi_dsi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
edp_bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
|
||||
wm8960: codec@1a {
|
||||
compatible = "wlf,wm8960";
|
||||
reg = <0x1a>;
|
||||
clocks = <&clock_12288>;
|
||||
clock-names = "mclk";
|
||||
#sound-dai-cells = <0>;
|
||||
wlf,shared-lrclk;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "nxp,pcf8523";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmif_a {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmout_a {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmif_b {
|
||||
pinctrl-0 = <&tdm_b_dout0_pins>, <&tdm_b_fs_pins>, <&tdm_b_sclk_pins>, <&tdm_b_din1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD1>,
|
||||
<&clkc_audio AUD_CLKID_TDM_LRCLK_PAD1>;
|
||||
assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_B_SCLK>,
|
||||
<&clkc_audio AUD_CLKID_MST_B_LRCLK>;
|
||||
assigned-clock-rates = <0>, <0>;
|
||||
};
|
||||
|
||||
&tdmin_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&toddr_a {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&toddr_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&toddr_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tohdmitx {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
dr_mode = "host";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
108
arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso
Normal file
108
arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/g12a-clkc.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/*
|
||||
* Enable Khadas TS050 DSI Panel + Touch Controller
|
||||
* on Khadas VIM3 (A311D) and VIM3L (S905D3)
|
||||
*/
|
||||
|
||||
&{/} {
|
||||
panel_backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm_AO_cd 0 25000 0>;
|
||||
brightness-levels = <0 255>;
|
||||
num-interpolated-steps = <255>;
|
||||
default-brightness-level = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
touch-controller@38 {
|
||||
compatible = "edt,edt-ft5206";
|
||||
reg = <0x38>;
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
interrupts = <IRQID_GPIOA_5 IRQ_TYPE_EDGE_FALLING>;
|
||||
reset-gpios = <&gpio_expander 6 GPIO_ACTIVE_LOW>;
|
||||
touchscreen-size-x = <1080>;
|
||||
touchscreen-size-y = <1920>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
assigned-clocks = <&clkc CLKID_GP0_PLL>,
|
||||
<&clkc CLKID_MIPI_DSI_PXCLK_SEL>,
|
||||
<&clkc CLKID_MIPI_DSI_PXCLK>,
|
||||
<&clkc CLKID_CTS_ENCL_SEL>,
|
||||
<&clkc CLKID_VCLK2_SEL>;
|
||||
assigned-clock-parents = <0>,
|
||||
<&clkc CLKID_GP0_PLL>,
|
||||
<0>,
|
||||
<&clkc CLKID_VCLK2_DIV1>,
|
||||
<&clkc CLKID_GP0_PLL>;
|
||||
assigned-clock-rates = <960000000>,
|
||||
<0>,
|
||||
<960000000>,
|
||||
<0>,
|
||||
<0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "khadas,ts050";
|
||||
reset-gpios = <&gpio_expander 0 GPIO_ACTIVE_LOW>;
|
||||
enable-gpios = <&gpio_expander 1 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <&vcc_3v3>;
|
||||
backlight = <&panel_backlight>;
|
||||
reg = <0>;
|
||||
|
||||
port {
|
||||
mipi_in_panel: endpoint {
|
||||
remote-endpoint = <&mipi_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
mipi_out_panel: endpoint {
|
||||
remote-endpoint = <&mipi_in_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_analog_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm_AO_cd {
|
||||
pinctrl-0 = <&pwm_ao_c_6_pins>, <&pwm_ao_d_e_pins>;
|
||||
};
|
||||
|
|
@ -65,10 +65,15 @@ xtal: xtal-clk {
|
|||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
pwrc: power-controller {
|
||||
compatible = "amlogic,meson-s4-pwrc";
|
||||
#power-domain-cells = <1>;
|
||||
status = "okay";
|
||||
firmware {
|
||||
sm: secure-monitor {
|
||||
compatible = "amlogic,meson-gxbb-sm";
|
||||
|
||||
pwrc: power-controller {
|
||||
compatible = "amlogic,meson-s4-pwrc";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user