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PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC

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Configure PBus base address and address mask to allow the hw
to detect if a given address is accessible on PCIe controller.

Fixes: f6ab898356 ("PCI: mediatek-gen3: Add Airoha EN7581 support")
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20250225-en7581-pcie-pbus-csr-v4-2-24324382424a@kernel.org
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
This commit is contained in:
Lorenzo Bianconi 2025-02-25 09:04:07 +01:00 committed by Krzysztof Wilczyński
parent a1360a6a72
commit 249b782980
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GPG Key ID: 7C64768D3DE334E7
1 changed files with 27 additions and 1 deletions
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28
drivers/pci/controller/pcie-mediatek-gen3.c
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@ -15,6 +15,7 @@
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/msi.h>
#include <linux/of_device.h>
@ -24,6 +25,7 @@
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include "../pci.h"
@ -930,9 +932,13 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
{
struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
struct device *dev = pcie->dev;
struct resource_entry *entry;
struct regmap *pbus_regmap;
u32 val, args[2], size;
resource_size_t addr;
int err;
u32 val;
/*
* The controller may have been left out of reset by the bootloader
@ -944,6 +950,26 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
/* Wait for the time needed to complete the reset lines assert. */
msleep(PCIE_EN7581_RESET_TIME_MS);
/*
* Configure PBus base address and base address mask to allow the
* hw to detect if a given address is accessible on PCIe controller.
*/
pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
"mediatek,pbus-csr",
ARRAY_SIZE(args),
args);
if (IS_ERR(pbus_regmap))
return PTR_ERR(pbus_regmap);
entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
if (!entry)
return -ENODEV;
addr = entry->res->start - entry->offset;
regmap_write(pbus_regmap, args[0], lower_32_bits(addr));
size = lower_32_bits(resource_size(entry->res));
regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
/*
* Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
* requires PHY initialization and power-on before PHY reset deassert.