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arm64: dts: imx8mm: Explicitly set DSI_PHY_REF clock as a child of CLK_24M

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Since commit a0deedcc0c ("arm64: dts: imx8mm: Slow default video_pll1
clock rate") and commit 5fe6ec93f1 ("clk: imx8mm: Let
IMX8MM_CLK_LCDIF_PIXEL set parent rate") VIDEO_PLL1 is dynamically
programmed by CLK_LCDIF_PIXEL.

On imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso this results in a
VIDEO_PLL1 frequency of 68.2 MHz and DSI_PHY_REF of 17.05MHz (1/4).
Instead use the 24 MHz clock as parent for DSI PHY reference clock.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Alexander Stein 2026-03-13 08:10:23 +01:00 committed by Frank Li
parent 21f0002238
commit 248d61177b
1 changed files with 4 additions and 2 deletions
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6
arch/arm64/boot/dts/freescale/imx8mm.dtsi
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@ -1148,8 +1148,10 @@ mipi_dsi: dsi@32e10000 {
clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>;
assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_CLK_24M>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
status = "disabled";