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dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
The clock controller of the zx297520v3 Low Speed Peripherals is relatively clean. One register per device with gates, muxes and resets and for some devices a divider. There are even bits in the matrix controller to control propagation of clock lines down to LSP. The clocks are sorted by register address and I am convinced that the device list is complete. There are, however, a few more registers that are likely extra dividers for TDM and I2S devices. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Stefan Dösinger
Brian Masney
parent
574e62ac2d
commit
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/zte,zx297520v3-lspcrm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ZTE zx297520v3 SoC LSP clock and reset controller
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maintainers:
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- Stefan Dösinger <stefandoesinger@gmail.com>
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description: |
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This clock and reset controller controls low speed peripherals on the board.
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This is a relatively isolated subsystem containing UART, I2C, I2S and SPI
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devices. The controller is responsible for bringing the devices out of reset
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and enabling their clocks as needed.
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The controller receives its clock signals from the matrix controller, and
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these signals need to be declared as clock inputs.
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All available clocks are defined as preprocessor macros in the
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"include/dt-bindings/clock/zte,zx297520v3-clk.h" header. Resets are defined in
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the "include/dt-bindings/reset/zte,zx297520v3-reset.h" header.
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properties:
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compatible:
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const: zte,zx297520v3-lspcrm
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Main PLL divided by 5 output from matrixcrm (124.8 MHz)
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- description: Main PLL divided by 4 output from matrixcrm (156 MHz)
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- description: Main PLL divided by 6 output from matrixcrm (104 MHz)
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- description: Main PLL divided by 8 output from matrixcrm (78 MHz)
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- description: Main PLL divided by 12 output from matrixcrm (52 MHz)
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- description: Main oscillator output from matrixcrm (26 MHz)
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- description: Timer oscillator output from matrixcrm (32 kHz)
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- description: LSP pclk output from matrixcrm (26 MHz)
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- description: TDM wclk mux output from matrixcrm
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- description: DPLL divided by 4 output from matrixcrm (122.88 MHz)
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clock-names:
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items:
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- const: mpll-d5
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- const: mpll-d4
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- const: mpll-d6
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- const: mpll-d8
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- const: mpll-d12
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- const: osc26m
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- const: osc32k
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- const: pclk
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- const: tdm-wclk
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- const: dpll-d4
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resets:
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maxItems: 1
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/zte,zx297520v3-clk.h>
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#include <dt-bindings/reset/zte,zx297520v3-reset.h>
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clock-controller@1400000 {
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compatible = "zte,zx297520v3-lspcrm";
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reg = <0x01400000 0x100>;
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#clock-cells = <1>;
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clocks = <&matrixcrm ZX297520V3_LSP_MPLL_D5_WCLK>,
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<&matrixcrm ZX297520V3_LSP_MPLL_D4_WCLK>,
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<&matrixcrm ZX297520V3_LSP_MPLL_D6_WCLK>,
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<&matrixcrm ZX297520V3_LSP_MPLL_D8_WCLK>,
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<&matrixcrm ZX297520V3_LSP_MPLL_D12_WCLK>,
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<&matrixcrm ZX297520V3_LSP_OSC26M_WCLK>,
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<&matrixcrm ZX297520V3_LSP_OSC32K_WCLK>,
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<&matrixcrm ZX297520V3_LSP_PCLK>,
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<&matrixcrm ZX297520V3_LSP_TDM_WCLK>,
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<&matrixcrm ZX297520V3_LSP_DPLL_D4_WCLK>;
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clock-names = "mpll-d5", "mpll-d4", "mpll-d6", "mpll-d8", "mpll-d12",
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"osc26m", "osc32k", "pclk", "tdm-wclk", "dpll-d4";
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#reset-cells = <1>;
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resets = <&matrixcrm ZX297520V3_LSP_RESET>;
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};
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@ -3909,6 +3909,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Odd fixes
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F: Documentation/arch/arm/zte/
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F: Documentation/devicetree/bindings/arm/zte.yaml
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F: Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml
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F: Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml
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F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml
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F: arch/arm/boot/dts/zte/
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@ -114,4 +114,41 @@
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#define ZX297520V3_LTE_MODEM_WCLK 42
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#define ZX297520V3_LTE_MODEM_PCLK 43
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#define ZX297520V3_TIMER_L1_WCLK 0
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#define ZX297520V3_TIMER_L1_PCLK 1
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#define ZX297520V3_WDT_L2_WCLK 2
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#define ZX297520V3_WDT_L2_PCLK 3
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#define ZX297520V3_WDT_L3_WCLK 4
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#define ZX297520V3_WDT_L3_PCLK 5
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#define ZX297520V3_PWM_WCLK 6
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#define ZX297520V3_PWM_PCLK 7
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#define ZX297520V3_I2S0_WCLK 8
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#define ZX297520V3_I2S0_PCLK 9
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#define ZX297520V3_I2S1_WCLK 10
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#define ZX297520V3_I2S1_PCLK 11
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#define ZX297520V3_QSPI_WCLK 12
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#define ZX297520V3_QSPI_PCLK 13
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#define ZX297520V3_UART1_WCLK 14
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#define ZX297520V3_UART1_PCLK 15
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#define ZX297520V3_I2C1_WCLK 16
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#define ZX297520V3_I2C1_PCLK 17
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#define ZX297520V3_SPI0_WCLK 18
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#define ZX297520V3_SPI0_PCLK 19
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#define ZX297520V3_TIMER_LB_WCLK 20
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#define ZX297520V3_TIMER_LB_PCLK 21
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#define ZX297520V3_TIMER_LC_WCLK 22
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#define ZX297520V3_TIMER_LC_PCLK 23
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#define ZX297520V3_UART2_WCLK 24
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#define ZX297520V3_UART2_PCLK 25
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#define ZX297520V3_WDT_LE_WCLK 26
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#define ZX297520V3_WDT_LE_PCLK 27
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#define ZX297520V3_TIMER_LF_WCLK 28
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#define ZX297520V3_TIMER_LF_PCLK 29
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#define ZX297520V3_SPI1_WCLK 30
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#define ZX297520V3_SPI1_PCLK 31
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#define ZX297520V3_TIMER_L11_WCLK 32
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#define ZX297520V3_TIMER_L11_PCLK 33
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#define ZX297520V3_TDM_WCLK 34
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#define ZX297520V3_TDM_PCLK 35
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#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
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@ -40,4 +40,23 @@
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#define ZX297520V3_VOU_RESET 10
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#define ZX297520V3_LSP_RESET 11
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#define ZX297520V3_TIMER_L1_RESET 0
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#define ZX297520V3_WDT_L2_RESET 1
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#define ZX297520V3_WDT_L3_RESET 2
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#define ZX297520V3_PWM_RESET 3
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#define ZX297520V3_I2S0_RESET 4
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#define ZX297520V3_I2S1_RESET 5
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#define ZX297520V3_QSPI_RESET 6
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#define ZX297520V3_UART1_RESET 7
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#define ZX297520V3_I2C1_RESET 8
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#define ZX297520V3_SPI0_RESET 9
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#define ZX297520V3_TIMER_LB_RESET 10
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#define ZX297520V3_TIMER_LC_RESET 11
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#define ZX297520V3_UART2_RESET 12
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#define ZX297520V3_WDT_LE_RESET 13
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#define ZX297520V3_TIMER_LF_RESET 14
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#define ZX297520V3_SPI1_RESET 15
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#define ZX297520V3_TIMER_L11_RESET 16
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#define ZX297520V3_TDM_RESET 17
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#endif /* __DT_BINDINGS_RESET_ZX297520V3_H */
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