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drm/i915: Move VT-d alignment into plane->min_alignment()

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Currently we don't account for the VT-d alignment w/a in
plane->min_alignment() which means that panning inside a larger
framebuffer can still cause the plane SURF to be misaligned.
Fix the issue by moving the VT-d alignment w/a into
plane->min_alignment() itself (for the affected platforms).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250122151755.6928-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2025-01-22 17:17:51 +02:00
parent aa0a9861bf
commit 241d831213
5 changed files with 24 additions and 8 deletions
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10
drivers/gpu/drm/i915/display/i9xx_plane.c
View File

@ -780,9 +780,14 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane,
const struct drm_framebuffer *fb,
int color_plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
if (intel_plane_can_async_flip(plane, fb->modifier))
return 256 * 1024;
if (intel_scanout_needs_vtd_wa(i915))
return 256 * 1024;
switch (fb->modifier) {
case I915_FORMAT_MOD_X_TILED:
return 4 * 1024;
@ -798,9 +803,14 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane,
const struct drm_framebuffer *fb,
int color_plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
if (intel_plane_can_async_flip(plane, fb->modifier))
return 256 * 1024;
if (intel_scanout_needs_vtd_wa(i915))
return 256 * 1024;
switch (fb->modifier) {
case I915_FORMAT_MOD_X_TILED:
case DRM_FORMAT_MOD_LINEAR:

5
drivers/gpu/drm/i915/display/intel_cursor.c
View File

@ -372,6 +372,11 @@ static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane,
const struct drm_framebuffer *fb,
int color_plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
if (intel_scanout_needs_vtd_wa(i915))
return 256 * 1024;
return 4 * 1024; /* physical for i915/i945 */
}

8
drivers/gpu/drm/i915/display/intel_fb_pin.c
View File

@ -126,14 +126,6 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
return ERR_PTR(-EINVAL);
/* Note that the w/a also requires 64 PTE of padding following the
* bo. We currently fill all unused PTE with the shadow page and so
* we should always have valid PTE following the scanout preventing
* the VT-d warning.
*/
if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
alignment = 256 * 1024;
/*
* Global gtt pte registers are special registers which actually forward
* writes to a chunk of system memory. Which means that there is no risk

5
drivers/gpu/drm/i915/display/intel_sprite.c
View File

@ -980,6 +980,11 @@ static unsigned int g4x_sprite_min_alignment(struct intel_plane *plane,
const struct drm_framebuffer *fb,
int color_plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
if (intel_scanout_needs_vtd_wa(i915))
return 256 * 1024;
return 4 * 1024;
}

4
drivers/gpu/drm/i915/display/skl_universal_plane.c
View File

@ -645,6 +645,10 @@ static u32 skl_plane_min_alignment(struct intel_plane *plane,
if (color_plane != 0)
return 4 * 1024;
/*
* VT-d needs at least 256k alignment,
* but that's already covered below.
*/
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED: