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arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2

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First usb and third pcie controller on mt7988 need a xs-phy to work
properly.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250422132438.15735-8-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Frank Wunderlich 2025-04-22 15:24:30 +02:00 committed by AngeloGioacchino Del Regno
parent 97ba5f51c2
commit 2400b24dfe
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GPG Key ID: 9A3604CFAD978478
1 changed files with 36 additions and 0 deletions
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36
arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@ -334,6 +334,8 @@ usb@11190000 {
<&infracfg CLK_INFRA_133M_USB_HCK>,
<&infracfg CLK_INFRA_USB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
phys = <&xphyu2port0 PHY_TYPE_USB2>,
<&xphyu3port0 PHY_TYPE_USB3>;
status = "disabled";
};
@ -398,6 +400,9 @@ pcie2: pcie@11280000 {
pinctrl-0 = <&pcie2_pins>;
status = "disabled";
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
@ -548,6 +553,37 @@ tphyu3port0: usb-phy@11c50700 {
};
};
topmisc: system-controller@11d10084 {
compatible = "mediatek,mt7988-topmisc",
"syscon";
reg = <0 0x11d10084 0 0xff80>;
};
xs-phy@11e10000 {
compatible = "mediatek,mt7988-xsphy",
"mediatek,xsphy";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
xphyu2port0: usb-phy@11e10000 {
reg = <0 0x11e10000 0 0x400>;
clocks = <&infracfg CLK_INFRA_USB_UTMI>;
clock-names = "ref";
#phy-cells = <1>;
};
xphyu3port0: usb-phy@11e13000 {
reg = <0 0x11e13400 0 0x500>;
clocks = <&infracfg CLK_INFRA_USB_PIPE>;
clock-names = "ref";
#phy-cells = <1>;
mediatek,syscon-type = <&topmisc 0x194 0>;
};
};
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;