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phy: rockchip: naneng-combphy: use existing DT property check for rk3528

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The naneng-combphy driver already has DT property checks for
"rockchip,enable-ssc" and "rockchip,ext-refclk", use it for
the rk3528_combphy_cfg. Also aligned the indentation of the
rk3528_combphy_grfcfgs parameters (using tabs).

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20250910122000.951100-1-amadeus@jmu.edu.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Chukun Pan 2025-09-10 20:20:00 +08:00 committed by Vinod Koul
parent d10736db98
commit 23c3373af0
1 changed files with 5 additions and 7 deletions
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12
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@ -529,7 +529,7 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
return -EINVAL;
}
if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
if (priv->ext_refclk) {
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
@ -554,11 +554,9 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
if (priv->type == PHY_TYPE_PCIE) {
if (device_property_read_bool(priv->dev, "rockchip,enable-ssc"))
rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
}
if (priv->type == PHY_TYPE_PCIE && priv->enable_ssc)
rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
return 0;
}
@ -582,7 +580,7 @@ static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
/* pipe-grf */
.u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
.u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
};
static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {