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dt-bindings: PCI: xilinx-versal-cpm: Add PERST# and reset support

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Add the optional 'resets' property to manage the PCIe IP reset, and the
'reset-gpios' property on the Root Port child node for GPIO-based control
of the PCIe RP PERST# signal (assert/deassert). Both are optional to keep
backward compatibility with existing device trees.

Update the examples to show the reset controller and PERST# GPIO wiring.

Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260818153755.3801111-2-sai.krishna.musham@amd.com
This commit is contained in:
Sai Krishna Musham 2026-08-18 21:07:54 +05:30 committed by Manivannan Sadhasivam
parent cee9395acd
commit 23a2ecf60e
1 changed files with 38 additions and 0 deletions
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38
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
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@ -41,6 +41,10 @@ properties:
description:
Maps a Requester ID to an MSI controller and associated MSI sideband data.
resets:
description: Reset for the PCIe controller.
maxItems: 1
ranges:
maxItems: 2
@ -61,6 +65,17 @@ properties:
interrupt-controller: true
patternProperties:
'^pcie@[0-2],0$':
type: object
$ref: /schemas/pci/pci-pci-bridge.yaml#
properties:
reg:
maxItems: 1
unevaluatedProperties: false
required:
- reg
- reg-names
@ -76,6 +91,9 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/xlnx-versal-resets.h>
versal {
#address-cells = <2>;
#size-cells = <2>;
@ -99,6 +117,16 @@ examples:
reg = <0x0 0xfca10000 0x0 0x1000>,
<0x6 0x00000000 0x0 0x10000000>;
reg-names = "cpm_slcr", "cfg";
resets = <&versal_reset VERSAL_RST_PCIE_CORE0>;
pcie@0,0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
pcie_intc_0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@ -127,6 +155,16 @@ examples:
<0x06 0x00000000 0x00 0x1000000>,
<0x00 0xfce20000 0x00 0x1000000>;
reg-names = "cpm_slcr", "cfg", "cpm_csr";
resets = <&versal_reset VERSAL_RST_PCIE_CORE0>;
pcie@0,0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
pcie_intc_1: interrupt-controller {
#address-cells = <0>;