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pinctrl: airoha: fix AN7583 MDIO pin mux config

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an7583_mdio_pins[] pointed at pins 43/44 (I2C1_SDA/I2C1_SCL) instead of
pins 53/54 (MDC_0/MDIO_0 respectively GPIO 51/52). Also the MDIO function
group wrote GPIO_SGMII_MDIO_MODE_MASK (bit 13 of REG_GPIO_PON_MODE, an
unrelated SGMII MDIO mode) and GPIO_MDC_IO_MASTER_MODE_MODE (BIT(14),
an EN7581 specific bit from REG_GPIO_2ND_I2C_MODE).

Fix both by setting an7583_mdio_pins[] to { 53, 54 } and rewriting the
function group to clear AN7583_MDC_0_GPIO_MODE_MASK (bit 25) and
AN7583_MDIO_0_GPIO_MODE_MASK (bit 26) of REG_GPIO_PON_MODE. Both bits
are cleared by the hwinit at probe.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Daniel Schwierzeck 2026-08-07 01:05:51 +03:00 committed by Linus Walleij
parent 0562b05f4a
commit 239fd71600
1 changed files with 6 additions and 10 deletions
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16
drivers/pinctrl/airoha/pinctrl-airoha.c
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@ -724,7 +724,8 @@ static const int an7583_pon_tod_1pps_pins[] = { 32 };
static const int an7583_gsw_tod_1pps_pins[] = { 32 };
static const int an7583_sipo_pins[] = { 34, 35 };
static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
static const int an7583_mdio_pins[] = { 43, 44 };
static const int an7583_mdio_pins[] = { 53, 54 };
static const int an7583_mdio1_pins[] = { 43, 44 };
static const int an7583_uart2_pins[] = { 34, 35 };
static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
static const int an7583_hsuart_pins[] = { 30, 31 };
@ -809,6 +810,7 @@ static const struct pingroup an7583_pinctrl_groups[] = {
PINCTRL_PIN_GROUP("sipo", an7583_sipo),
PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
PINCTRL_PIN_GROUP("mdio", an7583_mdio),
PINCTRL_PIN_GROUP("mdio1", an7583_mdio1),
PINCTRL_PIN_GROUP("uart2", an7583_uart2),
PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
@ -1081,16 +1083,10 @@ static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
.regmap[0] = {
AIROHA_FUNC_MUX,
REG_GPIO_PON_MODE,
GPIO_SGMII_MDIO_MODE_MASK,
GPIO_SGMII_MDIO_MODE_MASK
AN7583_MDC_0_GPIO_MODE_MASK | AN7583_MDIO_0_GPIO_MODE_MASK,
0
},
.regmap[1] = {
AIROHA_FUNC_MUX,
REG_GPIO_SPI_CS1_MODE,
AN7583_GPIO_MDC_IO_MASTER_MODE_MASK,
AN7583_GPIO_MDC_IO_MASTER_MODE_MASK
},
.regmap_size = 2,
.regmap_size = 1,
},
};