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clk: thead: th1520-ap: Support setting PLL rates
TH1520 ships several PLLs that could operate in either integer or fractional mode. However, the TRM only lists a few configuration whose stability is considered guaranteed. Add a table-lookup rate determination logic to support PLL rate setting, and fill up frequency-configuration tables for AP-subsystem PLLs. Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Yao Zi <ziyao@disroot.org> Signed-off-by: Drew Fustini <fustini@kernel.org>
This commit is contained in:
Yao Zi
Drew Fustini
parent
b436f8a82a
commit
238cc6316a
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@ -22,6 +22,7 @@
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#define TH1520_PLL_REFDIV GENMASK(5, 0)
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#define TH1520_PLL_BYPASS BIT(30)
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#define TH1520_PLL_VCO_RST BIT(29)
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#define TH1520_PLL_DACPD BIT(25)
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#define TH1520_PLL_DSMPD BIT(24)
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#define TH1520_PLL_FRAC GENMASK(23, 0)
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#define TH1520_PLL_FRAC_BITS 24
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@ -72,9 +73,19 @@ struct ccu_div {
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struct ccu_common common;
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};
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struct ccu_pll_cfg {
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unsigned long freq;
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u32 fbdiv;
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u32 frac;
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u32 postdiv1;
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u32 postdiv2;
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};
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struct ccu_pll {
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struct ccu_common common;
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u32 lock_sts_mask;
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int cfgnum;
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const struct ccu_pll_cfg *cfgs;
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};
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#define TH_CCU_ARG(_shift, _width) \
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@ -391,17 +402,102 @@ static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
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return rate;
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}
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static const struct ccu_pll_cfg *ccu_pll_lookup_best_cfg(struct ccu_pll *pll,
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unsigned long rate)
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{
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unsigned long best_delta = ULONG_MAX;
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const struct ccu_pll_cfg *best_cfg;
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int i;
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for (i = 0; i < pll->cfgnum; i++) {
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const struct ccu_pll_cfg *cfg = &pll->cfgs[i];
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unsigned long delta;
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delta = abs_diff(cfg->freq, rate);
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if (delta < best_delta) {
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best_delta = delta;
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best_cfg = cfg;
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}
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}
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return best_cfg;
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}
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static int ccu_pll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct ccu_pll *pll = hw_to_ccu_pll(hw);
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req->rate = ccu_pll_lookup_best_cfg(pll, req->rate)->freq;
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return 0;
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}
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static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_pll *pll = hw_to_ccu_pll(hw);
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const struct ccu_pll_cfg *cfg;
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cfg = ccu_pll_lookup_best_cfg(pll, rate);
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ccu_pll_disable(hw);
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regmap_write(pll->common.map, pll->common.cfg0,
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FIELD_PREP(TH1520_PLL_REFDIV, 1) |
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FIELD_PREP(TH1520_PLL_FBDIV, cfg->fbdiv) |
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FIELD_PREP(TH1520_PLL_POSTDIV1, cfg->postdiv1) |
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FIELD_PREP(TH1520_PLL_POSTDIV2, cfg->postdiv2));
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regmap_update_bits(pll->common.map, pll->common.cfg1,
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TH1520_PLL_DACPD | TH1520_PLL_DSMPD |
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TH1520_PLL_FRAC,
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cfg->frac ? cfg->frac :
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TH1520_PLL_DACPD | TH1520_PLL_DSMPD);
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return ccu_pll_enable(hw);
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}
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static const struct clk_ops clk_pll_ops = {
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.disable = ccu_pll_disable,
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.enable = ccu_pll_enable,
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.is_enabled = ccu_pll_is_enabled,
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.recalc_rate = ccu_pll_recalc_rate,
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.determine_rate = ccu_pll_determine_rate,
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.set_rate = ccu_pll_set_rate,
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};
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static const struct clk_parent_data osc_24m_clk[] = {
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{ .index = 0 }
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};
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static const struct ccu_pll_cfg cpu_pll_cfgs[] = {
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{ 125000000, 125, 0, 6, 4 },
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{ 200000000, 125, 0, 5, 3 },
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{ 300000000, 125, 0, 5, 2 },
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{ 400000000, 100, 0, 3, 2 },
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{ 500000000, 125, 0, 6, 1 },
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{ 600000000, 125, 0, 5, 1 },
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{ 702000000, 117, 0, 4, 1 },
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{ 800000000, 100, 0, 3, 1 },
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{ 900000000, 75, 0, 2, 1 },
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{ 1000000000, 125, 0, 3, 1 },
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{ 1104000000, 92, 0, 2, 1 },
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{ 1200000000, 100, 0, 2, 1 },
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{ 1296000000, 108, 0, 2, 1 },
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{ 1404000000, 117, 0, 2, 1 },
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{ 1500000000, 125, 0, 2, 1 },
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{ 1608000000, 67, 0, 1, 1 },
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{ 1704000000, 71, 0, 1, 1 },
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{ 1800000000, 75, 0, 1, 1 },
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{ 1896000000, 79, 0, 1, 1 },
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{ 1992000000, 83, 0, 1, 1 },
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{ 2112000000, 88, 0, 1, 1 },
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{ 2208000000, 92, 0, 1, 1 },
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{ 2304000000, 96, 0, 1, 1 },
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{ 2400000000, 100, 0, 1, 1 },
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};
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static struct ccu_pll cpu_pll0_clk = {
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.common = {
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.clkid = CLK_CPU_PLL0,
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@ -413,6 +509,8 @@ static struct ccu_pll cpu_pll0_clk = {
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CLK_IS_CRITICAL),
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},
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.lock_sts_mask = BIT(1),
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.cfgnum = ARRAY_SIZE(cpu_pll_cfgs),
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.cfgs = cpu_pll_cfgs,
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};
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static struct ccu_pll cpu_pll1_clk = {
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@ -426,6 +524,16 @@ static struct ccu_pll cpu_pll1_clk = {
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CLK_IS_CRITICAL),
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},
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.lock_sts_mask = BIT(4),
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.cfgnum = ARRAY_SIZE(cpu_pll_cfgs),
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.cfgs = cpu_pll_cfgs,
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};
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static const struct ccu_pll_cfg gmac_pll_cfg = {
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.freq = 1000000000,
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.fbdiv = 125,
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.frac = 0,
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.postdiv1 = 3,
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.postdiv2 = 1,
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};
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static struct ccu_pll gmac_pll_clk = {
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@ -439,6 +547,8 @@ static struct ccu_pll gmac_pll_clk = {
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CLK_IS_CRITICAL),
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},
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.lock_sts_mask = BIT(3),
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.cfgnum = 1,
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.cfgs = &gmac_pll_cfg,
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};
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static const struct clk_hw *gmac_pll_clk_parent[] = {
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@ -449,6 +559,14 @@ static const struct clk_parent_data gmac_pll_clk_pd[] = {
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{ .hw = &gmac_pll_clk.common.hw }
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};
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static const struct ccu_pll_cfg video_pll_cfg = {
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.freq = 792000000,
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.fbdiv = 99,
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.frac = 0,
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.postdiv1 = 3,
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.postdiv2 = 1,
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};
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static struct ccu_pll video_pll_clk = {
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.common = {
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.clkid = CLK_VIDEO_PLL,
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@ -460,6 +578,8 @@ static struct ccu_pll video_pll_clk = {
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CLK_IS_CRITICAL),
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},
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.lock_sts_mask = BIT(7),
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.cfgnum = 1,
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.cfgs = &video_pll_cfg,
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};
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static const struct clk_hw *video_pll_clk_parent[] = {
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@ -470,6 +590,14 @@ static const struct clk_parent_data video_pll_clk_pd[] = {
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{ .hw = &video_pll_clk.common.hw }
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};
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static const struct ccu_pll_cfg dpu_pll_cfg = {
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.freq = 1188000000,
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.fbdiv = 99,
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.frac = 0,
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.postdiv1 = 2,
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.postdiv2 = 1,
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};
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static struct ccu_pll dpu0_pll_clk = {
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.common = {
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.clkid = CLK_DPU0_PLL,
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@ -481,6 +609,8 @@ static struct ccu_pll dpu0_pll_clk = {
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0),
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},
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.lock_sts_mask = BIT(8),
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.cfgnum = 1,
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.cfgs = &dpu_pll_cfg,
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};
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static const struct clk_hw *dpu0_pll_clk_parent[] = {
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@ -498,12 +628,22 @@ static struct ccu_pll dpu1_pll_clk = {
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0),
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},
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.lock_sts_mask = BIT(9),
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.cfgnum = 1,
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.cfgs = &dpu_pll_cfg,
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};
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static const struct clk_hw *dpu1_pll_clk_parent[] = {
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&dpu1_pll_clk.common.hw
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};
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static const struct ccu_pll_cfg tee_pll_cfg = {
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.freq = 792000000,
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.fbdiv = 99,
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.frac = 0,
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.postdiv1 = 3,
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.postdiv2 = 1,
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};
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static struct ccu_pll tee_pll_clk = {
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.common = {
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.clkid = CLK_TEE_PLL,
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@ -515,6 +655,8 @@ static struct ccu_pll tee_pll_clk = {
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CLK_IS_CRITICAL),
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},
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.lock_sts_mask = BIT(10),
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.cfgnum = 1,
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.cfgs = &tee_pll_cfg,
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};
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static const struct clk_parent_data c910_i0_parents[] = {
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