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input: qcom-hv-haptics: update LRA frequency detection sequence

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Update following settings in LRA frequency detection sequence according
to HW recommendation:
  1) Increase to 6 drive cycles before enabling High-Z period for auto
     resonance config.
  2) Disable adaptive drive duty function.

Change-Id: I551974603c99fcdad5d38fdef6edf15746c0033e
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
This commit is contained in:
Fenglin Wu 2021-03-01 13:35:31 +08:00 committed by David Collins
parent f0d2102bf1
commit 23895eba21
1 changed files with 16 additions and 2 deletions
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18
drivers/input/misc/qcom-hv-haptics.c
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@ -116,13 +116,16 @@
#define RC_CLK_CAL_COUNT_LSB_MASK GENMASK(7, 0)
#define HAP_CFG_DRV_DUTY_CFG_REG 0x60
#define ADT_DRV_DUTY_EN_BIT BIT(7)
#define HAP_CFG_ADT_DRV_DUTY_CFG_REG 0x61
#define HAP_CFG_ZX_WIND_CFG_REG 0x62
#define HAP_CFG_AUTORES_CFG_REG 0x63
#define AUTORES_EN_BIT BIT(7)
#define AUTORES_EN_DLY_MASK GENMASK(5, 2)
#define AUTORES_EN_DLY_1_CYCLE 0x2
#define AUTORES_EN_DLY(cycles) ((cycles) * 2)
#define AUTORES_EN_DLY_6_CYCLES AUTORES_EN_DLY(6)
#define AUTORES_EN_DLY_SHIFT 2
#define AUTORES_ERR_WINDOW_MASK GENMASK(1, 0)
#define AUTORES_ERR_WINDOW_12P5_PERCENT 0x0
@ -4086,11 +4089,16 @@ static int haptics_detect_lra_frequency(struct haptics_chip *chip)
rc = haptics_masked_write(chip, chip->cfg_addr_base,
HAP_CFG_AUTORES_CFG_REG, AUTORES_EN_BIT |
AUTORES_EN_DLY_MASK | AUTORES_ERR_WINDOW_MASK,
AUTORES_EN_DLY_1_CYCLE << AUTORES_EN_DLY_SHIFT
AUTORES_EN_DLY_6_CYCLES << AUTORES_EN_DLY_SHIFT
| AUTORES_ERR_WINDOW_50_PERCENT | AUTORES_EN_BIT);
if (rc < 0)
return rc;
rc = haptics_masked_write(chip, chip->cfg_addr_base,
HAP_CFG_DRV_DUTY_CFG_REG, ADT_DRV_DUTY_EN_BIT, 0);
if (rc < 0)
goto restore;
rc = haptics_config_openloop_lra_period(chip, chip->config.t_lra_us);
if (rc < 0)
goto restore;
@ -4143,6 +4151,12 @@ static int haptics_detect_lra_frequency(struct haptics_chip *chip)
rc = haptics_write(chip, chip->cfg_addr_base,
HAP_CFG_AUTORES_CFG_REG, &autores_cfg, 1);
if (rc < 0)
return rc;
rc = haptics_masked_write(chip, chip->cfg_addr_base,
HAP_CFG_DRV_DUTY_CFG_REG, ADT_DRV_DUTY_EN_BIT,
ADT_DRV_DUTY_EN_BIT);
return rc;
}