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* Fix TDX port I/O bugs

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-----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEV76QKkVc4xCGURexaDWVMHDJkrAFAmqEdMcACgkQaDWVMHDJ
 krBa6BAAuDNE9VuX+ctu/H5dQUhnIrUWAiqWRPAeCRU4slW1j64Y/77VTrLxPrdq
 YbhsaMaDXOPU8sRfdJ5fDyLT9jFnIfxi0qNXxCJXYljK1jAqGx7C1+cQY5PjNE2F
 avZSDQ3lUvGVg4jjeZtFRZJC5UMUFyIG7dXbp2KR5fvPdRfO9YaWrXmSVEw2zSPT
 j/utLS3I3hx/MYgrRzqRDdpqh0rghych3sCGsQlJ2+YX9NYmviHCCwy10D7OTXsl
 uRDQfEl5IOhPDJwIiM/FuY5vmoB3UCSWrMQMkE2RxZR01HS7u0Pw4Q3MdY4BlCTb
 6Bzq24W4KUvF1RBFF2wth4RqcERtw48ONhuzdHEF8SCwroDiydeX/vzVfxvN0+1Y
 EKm3APx4SfWpmPaNlYkct5OPmXoUqQItKDtJGqZfnR68HLiRi2rhHmwLujlnPiSV
 tuChn01RyTtUVHiF6dcrnRxOXAaLn7AQ5QK7mW7JhmuNi9yEaf1xR1BMF5W8nseq
 VZSUWRyK3L0HgdZyeW1bTBbjaTcrdBaPv8a20Xsj7CvQP5NCTnue487LaKXWclt9
 BCQuUPofJnVHddrEU7mJvAHAemR+Rca9wS83TV2d6e/5doaujt6+deJVGELkQpBL
 lioc+xI+dIQkJ5OLkdmm8fU76kQAEhthS+KzBmlqjHhVZnzDKuk=
 =rzxt
 -----END PGP SIGNATURE-----

Merge tag 'x86_tdx_for_7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 TDX updates from Dave Hansen:
 "TDX guests cause #VE exceptions whenever they do port I/O. The guest
  then does some instruction decoding and makes a call up to the host
  for help. That decoding had a couple of bugs.

  Fix those bugs. Use an existing and now shared KVM helper for one of
  them"

* tag 'x86_tdx_for_7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/tdx: Fix zero-extension for 32-bit port I/O
  x86/insn-eval: Move assign_register() out of KVM as insn_assign_reg()
  x86/tdx: Fix off-by-one in port I/O handling
This commit is contained in:
Linus Torvalds 2026-08-18 17:41:36 -07:00
commit 2385c8b47b
3 changed files with 44 additions and 28 deletions
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10
arch/x86/coco/tdx/tdx.c
View File

@ -694,8 +694,8 @@ static bool handle_in(struct pt_regs *regs, int size, int port)
.r13 = PORT_READ,
.r14 = port,
};
u64 mask = GENMASK(BITS_PER_BYTE * size, 0);
bool success;
u64 val;
/*
* Emulate the I/O read via hypercall. More info about ABI can be found
@ -703,18 +703,16 @@ static bool handle_in(struct pt_regs *regs, int size, int port)
* "TDG.VP.VMCALL<Instruction.IO>".
*/
success = !__tdx_hypercall(&args);
val = success ? args.r11 : 0;
/* Update part of the register affected by the emulated instruction */
regs->ax &= ~mask;
if (success)
regs->ax |= args.r11 & mask;
insn_assign_reg(&regs->ax, val, size);
return success;
}
static bool handle_out(struct pt_regs *regs, int size, int port)
{
u64 mask = GENMASK(BITS_PER_BYTE * size, 0);
u64 mask = GENMASK(BITS_PER_BYTE * size - 1, 0);
/*
* Emulate the I/O write via hypercall. More info about ABI can be found

36
arch/x86/include/asm/insn-eval.h
View File

@ -9,6 +9,7 @@
#include <linux/compiler.h>
#include <linux/bug.h>
#include <linux/err.h>
#include <asm/insn.h>
#include <asm/ptrace.h>
#define INSN_CODE_SEG_ADDR_SZ(params) ((params >> 4) & 0xf)
@ -46,4 +47,39 @@ enum insn_mmio_type insn_decode_mmio(struct insn *insn, int *bytes);
bool insn_is_nop(struct insn *insn);
/*
* Write @val into *@reg following the x86 rules for writes to
* general-purpose registers (Intel SDM Vol. 1, "General-Purpose
* Registers in 64-Bit Mode"): an 8- or 16-bit write leaves the rest of
* the register untouched, a 32-bit write zero-extends the result into
* the upper 32 bits, and a 64-bit write replaces the whole register.
*
* @bytes is the width of the write, not a property of the instruction:
* an instruction that, say, sign-extends a 32-bit immediate into a
* 64-bit register does a 64-bit write here.
*
* @reg need not be 8-byte aligned: KVM's instruction emulator offsets
* the pointer by one byte to address the high-byte registers (AH, CH,
* DH, BH). Use narrow stores for the sub-word cases so the access
* width matches @bytes and the adjacent bytes are left alone.
*/
static inline void insn_assign_reg(unsigned long *reg, u64 val, int bytes)
{
switch (bytes) {
case 1:
*(u8 *)reg = (u8)val;
break;
case 2:
*(u16 *)reg = (u16)val;
break;
case 4:
/* A 32-bit write zero-extends into the upper 32 bits. */
*reg = (u32)val;
break;
case 8:
*reg = val;
break;
}
}
#endif /* _ASM_X86_INSN_EVAL_H */

26
arch/x86/kvm/emulate.c
View File

@ -24,6 +24,7 @@
#include "kvm_emulate.h"
#include <linux/stringify.h>
#include <asm/debugreg.h>
#include <asm/insn-eval.h>
#include <asm/nospec-branch.h>
#include <asm/ibt.h>
#include <asm/text-patching.h>
@ -439,25 +440,6 @@ static void assign_masked(ulong *dest, ulong src, ulong mask)
*dest = (*dest & ~mask) | (src & mask);
}
static void assign_register(unsigned long *reg, u64 val, int bytes)
{
/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
switch (bytes) {
case 1:
*(u8 *)reg = (u8)val;
break;
case 2:
*(u16 *)reg = (u16)val;
break;
case 4:
*reg = (u32)val;
break; /* 64b: zero-extend */
case 8:
*reg = val;
break;
}
}
static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
{
return (1UL << (ctxt->ad_bytes << 3)) - 1;
@ -505,7 +487,7 @@ register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
{
ulong *preg = reg_rmw(ctxt, reg);
assign_register(preg, *preg + inc, ctxt->ad_bytes);
insn_assign_reg(preg, *preg + inc, ctxt->ad_bytes);
}
static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
@ -1767,7 +1749,7 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
static void write_register_operand(struct operand *op)
{
return assign_register(op->addr.reg, op->val, op->bytes);
return insn_assign_reg(op->addr.reg, op->val, op->bytes);
}
static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
@ -2008,7 +1990,7 @@ static int em_popa(struct x86_emulate_ctxt *ctxt)
rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
if (rc != X86EMUL_CONTINUE)
break;
assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
insn_assign_reg(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
--reg;
}
return rc;