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drm/amd/display: refactor riommu invalidation wa
[Why] A cleaner solution, only done once on boot. [How] Remove previous workaround and configure an extra vmid one time on boot Reviewed-by: Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -610,20 +610,3 @@ bool dcn31_is_abm_supported(struct dc *dc,
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}
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return false;
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}
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static void apply_riommu_invalidation_wa(struct dc *dc)
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{
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struct dce_hwseq *hws = dc->hwseq;
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if (!hws->wa.early_riommu_invalidation)
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return;
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REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, 0);
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}
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void dcn31_init_pipes(struct dc *dc, struct dc_state *context)
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{
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dcn10_init_pipes(dc, context);
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apply_riommu_invalidation_wa(dc);
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}
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@ -104,7 +104,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
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};
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static const struct hwseq_private_funcs dcn31_private_funcs = {
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.init_pipes = dcn31_init_pipes,
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.init_pipes = dcn10_init_pipes,
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.update_plane_addr = dcn20_update_plane_addr,
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.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
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.update_mpcc = dcn20_update_mpcc,
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@ -1302,7 +1302,6 @@ static struct dce_hwseq *dcn31_hwseq_create(
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hws->regs = &hwseq_reg;
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hws->shifts = &hwseq_shift;
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hws->masks = &hwseq_mask;
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hws->wa.early_riommu_invalidation = true;
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}
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return hws;
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}
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@ -41,7 +41,6 @@ struct dce_hwseq_wa {
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bool DEGVIDCN10_254;
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bool DEGVIDCN21;
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bool disallow_self_refresh_during_multi_plane_transition;
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bool early_riommu_invalidation;
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};
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struct hwseq_wa_state {
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