drm/amd/display: refactor riommu invalidation wa

[Why]
A cleaner solution, only done once on boot.

[How]
Remove previous workaround and configure an extra
vmid one time on boot

Reviewed-by: Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Yang 2021-07-09 17:47:39 -04:00 committed by Alex Deucher
parent 90a9266269
commit 234b4fd917
4 changed files with 1 additions and 20 deletions

View File

@ -610,20 +610,3 @@ bool dcn31_is_abm_supported(struct dc *dc,
}
return false;
}
static void apply_riommu_invalidation_wa(struct dc *dc)
{
struct dce_hwseq *hws = dc->hwseq;
if (!hws->wa.early_riommu_invalidation)
return;
REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, 0);
}
void dcn31_init_pipes(struct dc *dc, struct dc_state *context)
{
dcn10_init_pipes(dc, context);
apply_riommu_invalidation_wa(dc);
}

View File

@ -104,7 +104,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
};
static const struct hwseq_private_funcs dcn31_private_funcs = {
.init_pipes = dcn31_init_pipes,
.init_pipes = dcn10_init_pipes,
.update_plane_addr = dcn20_update_plane_addr,
.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
.update_mpcc = dcn20_update_mpcc,

View File

@ -1302,7 +1302,6 @@ static struct dce_hwseq *dcn31_hwseq_create(
hws->regs = &hwseq_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
hws->wa.early_riommu_invalidation = true;
}
return hws;
}

View File

@ -41,7 +41,6 @@ struct dce_hwseq_wa {
bool DEGVIDCN10_254;
bool DEGVIDCN21;
bool disallow_self_refresh_during_multi_plane_transition;
bool early_riommu_invalidation;
};
struct hwseq_wa_state {