From 23305c88fa765f50a33cdc1cf35a93f0ac7755fa Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 24 Apr 2026 11:15:04 +0800 Subject: [PATCH] drm/amdgpu: add mec FW support for silicon rev 0 MEC will have the specific FW binary for silicon rev 0. Signed-off-by: Shiwu Zhang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 606106ddf99d..41b92d068517 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -549,9 +549,15 @@ static int gfx_v12_1_init_microcode(struct amdgpu_device *adev) goto out; } - err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, - AMDGPU_UCODE_REQUIRED, - "amdgpu/%s_mec.bin", ucode_prefix); + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && + adev->rev_id == 0) + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, + AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_mec_1.bin", ucode_prefix); + else + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, + AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_mec.bin", ucode_prefix); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);