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wifi: mt76: mt7996: update WFSYS reset flow for MT7990 chipsets

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Skip WFSYS reset during bootup for MT7990 chipsets; only reset if L0.5
recovery is triggered.
Without this fix, the following kernel error may occur:
Internal error: synchronous external abort.

Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20260312095724.2117448-3-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Peter Chiu 2026-03-12 17:57:21 +08:00 committed by Felix Fietkau
parent cf909557c1
commit 22f9abaf36
2 changed files with 34 additions and 3 deletions
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29
drivers/net/wireless/mediatek/mt76/mt7996/init.c
View File

@ -791,11 +791,34 @@ static void mt7996_init_work(struct work_struct *work)
void mt7996_wfsys_reset(struct mt7996_dev *dev)
{
mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
if (!is_mt7990(&dev->mt76)) {
mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
msleep(20);
mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
msleep(20);
return;
}
if (!dev->recovery.hw_full_reset)
return;
mt76_set(dev, MT_WF_SUBSYS_RST,
MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT |
MT_WF_SUBSYS_RST_BYPASS_WFDMA_SLP_PROT |
MT_WF_SUBSYS_RST_BYPASS_WFDMA2_SLP_PROT);
mt76_rmw(dev, MT_WF_SUBSYS_RST,
MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE,
u32_encode_bits(0x20, MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE));
mt76_clear(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK);
mt76_set(dev, MT_WF_SUBSYS_RST, MT_WF_SUBSYS_RST_WHOLE_PATH_RST);
msleep(20);
mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
msleep(20);
if (mt76_poll(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK, 0x1a, 1000))
return;
dev_err(dev->mt76.dev, "wfsys reset fail\n");
}
static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev)

8
drivers/net/wireless/mediatek/mt76/mt7996/regs.h
View File

@ -736,7 +736,15 @@ enum offs_rev {
#define MT_HW_REV 0x70010204
#define MT_HW_REV1 0x8a00
#define MT_WF_L05_RST 0x70028550
#define MT_WF_L05_RST_WF_RST_MASK GENMASK(4, 0)
#define MT_WF_SUBSYS_RST 0x70028600
#define MT_WF_SUBSYS_RST_WHOLE_PATH_RST BIT(0)
#define MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT BIT(5)
#define MT_WF_SUBSYS_RST_BYPASS_WFDMA_SLP_PROT BIT(6)
#define MT_WF_SUBSYS_RST_BYPASS_WFDMA2_SLP_PROT BIT(16)
#define MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE GENMASK(15, 8)
/* PCIE MAC */
#define MT_PCIE_MAC_BASE 0x74030000