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drm/xe: Sort again the info flags
Those flags are supposed to be kept sorted alphabetically. Unfortunately it's a constant battle as new flags are added to the end or at random places. Sort it again. v2: Include the other non-has_* 1-bit flags in the sort v3: Add comment to keep flags sorted Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> # v1 Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241120195710.3447100-1-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
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@ -294,14 +294,24 @@ struct xe_device {
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/** @info.va_bits: Maximum bits of a virtual address */
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u8 va_bits;
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/** @info.is_dgfx: is discrete device */
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u8 is_dgfx:1;
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/** @info.has_asid: Has address space ID */
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u8 has_asid:1;
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/*
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* Keep all flags below alphabetically sorted
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*/
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/** @info.force_execlist: Forced execlist submission */
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u8 force_execlist:1;
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/** @info.has_asid: Has address space ID */
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u8 has_asid:1;
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/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
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u8 has_atomic_enable_pte_bit:1;
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/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
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u8 has_device_atomics_on_smem:1;
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/** @info.has_flat_ccs: Whether flat CCS metadata is used */
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u8 has_flat_ccs:1;
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/** @info.has_heci_cscfi: device has heci cscfi */
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u8 has_heci_cscfi:1;
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/** @info.has_heci_gscfi: device has heci gscfi */
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u8 has_heci_gscfi:1;
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/** @info.has_llc: Device has a shared CPU+GPU last level cache */
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u8 has_llc:1;
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/** @info.has_mmio_ext: Device has extra MMIO address range */
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@ -312,6 +322,8 @@ struct xe_device {
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u8 has_sriov:1;
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/** @info.has_usm: Device has unified shared memory support */
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u8 has_usm:1;
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/** @info.is_dgfx: is discrete device */
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u8 is_dgfx:1;
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/**
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* @info.probe_display: Probe display hardware. If set to
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* false, the driver will behave as if there is no display
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@ -321,20 +333,12 @@ struct xe_device {
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* state the firmware or bootloader left it in.
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*/
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u8 probe_display:1;
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/** @info.skip_guc_pc: Skip GuC based PM feature init */
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u8 skip_guc_pc:1;
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/** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */
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u8 skip_mtcfg:1;
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/** @info.skip_pcode: skip access to PCODE uC */
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u8 skip_pcode:1;
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/** @info.has_heci_gscfi: device has heci gscfi */
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u8 has_heci_gscfi:1;
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/** @info.has_heci_cscfi: device has heci cscfi */
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u8 has_heci_cscfi:1;
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/** @info.skip_guc_pc: Skip GuC based PM feature init */
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u8 skip_guc_pc:1;
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/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
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u8 has_atomic_enable_pte_bit:1;
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/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
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u8 has_device_atomics_on_smem:1;
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} info;
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/** @irq: device interrupt state */
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