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drm/xe/irq: Untangle postinstall functions

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The xe_irq_postinstall() never actually gets called after installing the
interrupt handler.  This oversight seems to get papered over due to the
fact that the (misnamed) xe_gt_irq_postinstall does more than it really
should and gets called in the middle of the GT initialization.  The
callstack for postinstall is also a bit muddled with top-level device
interrupt enablement happening within platform-specific functions called
from the per-tile xe_gt_irq_postinstall() function.

Clean this all up by adding the missing call to xe_irq_postinstall()
after installing the interrupt handler and pull top-level irq enablement
up to xe_irq_postinstall where we'd expect it to be.

The xe_gt_irq_postinstall() function is still a bit misnamed here; an
upcoming patch will refocus its purpose and rename it.

v2:
 - Squash in patch to actually call xe_irq_postinstall() after
   installing the interrupt handler.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230601215244.678611-25-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-06-01 14:52:37 -07:00 committed by Rodrigo Vivi
parent 80d6e5874a
commit 22a2223601
1 changed files with 9 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
drivers/gpu/drm/xe/xe_irq.c
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@ -121,7 +121,7 @@ static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
xe_mmio_read32(mmio, GFX_MSTR_IRQ);
}
static void gt_irq_postinstall(struct xe_tile *tile)
void xe_gt_irq_postinstall(struct xe_tile *tile)
{
struct xe_device *xe = tile_to_xe(tile);
struct xe_gt *mmio = tile->primary_gt;
@ -180,15 +180,6 @@ static void gt_irq_postinstall(struct xe_tile *tile)
xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
}
static void xelp_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
{
/* TODO: PCH */
gt_irq_postinstall(tile);
xelp_intr_enable(xe, true);
}
static u32
gt_engine_identity(struct xe_device *xe,
struct xe_gt *mmio,
@ -361,14 +352,6 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
}
static void dg1_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
{
gt_irq_postinstall(tile);
if (tile->id == 0)
dg1_intr_enable(xe, true);
}
/*
* Top-level interrupt handler for Xe_LP+ and beyond. These platforms have
* a "master tile" interrupt register which must be consulted before the
@ -503,16 +486,6 @@ static void xe_irq_reset(struct xe_device *xe)
mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
}
void xe_gt_irq_postinstall(struct xe_tile *tile)
{
struct xe_device *xe = tile_to_xe(tile);
if (GRAPHICS_VERx100(xe) >= 1210)
dg1_irq_postinstall(xe, tile);
else
xelp_irq_postinstall(xe, tile);
}
static void xe_irq_postinstall(struct xe_device *xe)
{
struct xe_tile *tile;
@ -527,6 +500,12 @@ static void xe_irq_postinstall(struct xe_device *xe)
*/
unmask_and_enable(xe_device_get_root_tile(xe),
GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
/* Enable top-level interrupts */
if (GRAPHICS_VERx100(xe) >= 1210)
dg1_intr_enable(xe, true);
else
xelp_intr_enable(xe, true);
}
static irq_handler_t xe_irq_handler(struct xe_device *xe)
@ -577,6 +556,8 @@ int xe_irq_install(struct xe_device *xe)
return err;
}
xe_irq_postinstall(xe);
err = drmm_add_action_or_reset(&xe->drm, irq_uninstall, xe);
if (err)
return err;