From ca588531ca4a0b93423705f973e60116fb0bc51d Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Tue, 11 Aug 2026 11:35:15 -0700 Subject: [PATCH 01/30] mips: rb532: use devm_platform_ioremap_resource in gpio probe Replace the platform_get_resource()/devm_ioremap_resource() pair with the devm_platform_ioremap_resource() helper and drop the now-unused struct resource pointer and NULL check. Assisted-by: opencode:deepseek-v4-flash-free Signed-off-by: Rosen Penev Signed-off-by: Thomas Bogendoerfer --- arch/mips/rb532/gpio.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 49e1a15a3827..458895a9fb25 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -192,13 +192,8 @@ EXPORT_SYMBOL(rb532_gpio_set_func); static int rb532_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct resource *res; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; - - rb532_gpio_chip->regbase = devm_ioremap_resource(dev, res); + rb532_gpio_chip->regbase = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rb532_gpio_chip->regbase)) return PTR_ERR(rb532_gpio_chip->regbase); From 7c582918e739632d32275dbd1952dd8c5d4b9b38 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2026 12:05:15 +0200 Subject: [PATCH 02/30] MIPS: Alchemy: clock: Make sure clk_init_data is fully initialized The clk_init_data structure contains several mutually-exclusive members for different methods to specify the possible parents of a clock, prompting drivers to initialize only the members they need. However, not initializing all members may cause subtle issues, which are only exposed when CONFIG_INIT_STACK_ALL_PATTERN or CONFIG_INIT_STACK_NONE is enabled. Make sure all members are fully initialized, to avoid such bugs, and to prevent future breakage when converting drivers to a different method for specifying the parents. Signed-off-by: Geert Uytterhoeven Reviewed-by: Brian Masney Signed-off-by: Thomas Bogendoerfer --- arch/mips/alchemy/common/clock.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c index 62a7304ff35f..b5d2cbb7c69e 100644 --- a/arch/mips/alchemy/common/clock.c +++ b/arch/mips/alchemy/common/clock.c @@ -150,7 +150,7 @@ static const struct clk_ops alchemy_clkops_cpu = { static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name, int ctype) { - struct clk_init_data id; + struct clk_init_data id = {}; struct clk_hw *h; struct clk *clk; @@ -245,7 +245,7 @@ static struct clk __init *alchemy_clk_setup_aux(const char *parent_name, char *name, int maxmult, unsigned long reg) { - struct clk_init_data id; + struct clk_init_data id = {}; struct clk *c; struct alchemy_auxpll_clk *a; @@ -754,7 +754,7 @@ static const char * const alchemy_clk_fgen_names[] = { static int __init alchemy_clk_init_fgens(int ctype) { struct clk *c; - struct clk_init_data id; + struct clk_init_data id = {}; struct alchemy_fgcs_clk *a; unsigned long v; int i, ret; @@ -959,9 +959,9 @@ static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 }; /* Au1300 */ static int __init alchemy_clk_setup_imux(int ctype) { + struct clk_init_data id = {}; struct alchemy_fgcs_clk *a; const char * const *names; - struct clk_init_data id; unsigned long v; int i, ret, *dt; struct clk *c; From caa81690f051433a1f131191573478ca5fe72af1 Mon Sep 17 00:00:00 2001 From: Hemanth Selam Date: Fri, 4 Sep 2026 18:19:19 +0530 Subject: [PATCH 03/30] MIPS: fix typos in comments Fix typos in comments, reported by scripts/checkpatch.pl using the misspelling list in scripts/spelling.txt. Only touches comments, no code changes. Assisted-by: Cursor:claude-opus-5 Signed-off-by: Hemanth Selam Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-loongson64/boot_param.h | 2 +- arch/mips/n64/init.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h index 3a11ce85762b..3e5c2b3a7f9b 100644 --- a/arch/mips/include/asm/mach-loongson64/boot_param.h +++ b/arch/mips/include/asm/mach-loongson64/boot_param.h @@ -24,7 +24,7 @@ struct efi_memory_map_loongson { u16 vers; /* version of efi_memory_map */ u32 nr_map; /* number of memory_maps */ - u32 mem_freq; /* memory frequence */ + u32 mem_freq; /* memory frequency */ struct mem_map { u32 node_id; /* node_id which memory attached to */ u32 mem_type; /* system memory, pci memory, pci io, etc. */ diff --git a/arch/mips/n64/init.c b/arch/mips/n64/init.c index 66ec28ab41f3..ddbd7d1224d3 100644 --- a/arch/mips/n64/init.c +++ b/arch/mips/n64/init.c @@ -20,7 +20,7 @@ #define IO_MEM_RESOURCE_END 0x1fffffffUL /* - * System-specifc irq names for clarity + * System-specific irq names for clarity */ #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) From 80532a8fbab8414795dc0f4a34bb65af23ec05e2 Mon Sep 17 00:00:00 2001 From: Hemanth Selam Date: Fri, 4 Sep 2026 18:19:20 +0530 Subject: [PATCH 04/30] MIPS: fix repeated words in comments Drop words accidentally written twice, reported by checkpatch.pl as a possible repeated word. Only touches comments, no code changes. Assisted-by: Cursor:claude-opus-5 Signed-off-by: Hemanth Selam Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/octeon-memcpy.S | 2 +- arch/mips/lib/memcpy.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S index fef0c6de3fa1..fb27126afc56 100644 --- a/arch/mips/cavium-octeon/octeon-memcpy.S +++ b/arch/mips/cavium-octeon/octeon-memcpy.S @@ -60,7 +60,7 @@ * 3- (dst - src) == (dst_entry - src_entry), * The _entry suffix denotes values when __copy_user was called. * - * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user + * (1) is set up by uaccess.h and maintained by not writing AT in copy_user * (2) is met by incrementing src by the number of bytes copied * (3) is met by not doing loads between a pair of increments of dst and src * diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S index 84f85aba6f4b..49408c0049f2 100644 --- a/arch/mips/lib/memcpy.S +++ b/arch/mips/lib/memcpy.S @@ -79,7 +79,7 @@ * 3- (dst - src) == (dst_entry - src_entry), * The _entry suffix denotes values when __copy_user was called. * - * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user + * (1) is set up by uaccess.h and maintained by not writing AT in copy_user * (2) is met by incrementing src by the number of bytes copied * (3) is met by not doing loads between a pair of increments of dst and src * From 9a486d67423ea2f95d1f1b085a981f8c33c45452 Mon Sep 17 00:00:00 2001 From: Orgad Shaneh Date: Tue, 15 Sep 2026 07:12:44 +0000 Subject: [PATCH 05/30] MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX The L2 helpers pick between the OCTEON II and the CN3XXX/CN5XXX register model with OCTEON_IS_MODEL(OCTEON_CN63XX), which matches the CN63XX only. Every other OCTEON II part - CN66XX, CN68XX, CN61XX - takes the CN3XXX/CN5XXX branch and touches registers that do not exist on it: L2C_DBG, L2C_LCKBASE, L2C_LCKOFF and L2C_SPAR4 instead of the LCKL2 cache operation, the L2C_WPAR_{PPX,IOBX} way-partitioning registers and L2C_TADX_TAG. On a CN6635 board cvmx_l2c_lock_line(), called from prom_init() under CONFIG_CAVIUM_OCTEON_LOCK_L2 to lock the TLB refill and exception vectors, therefore went through L2C_DBG/L2C_LCKBASE. Whatever those writes hit inside the L2 controller left it silently dropping stores to DRAM above 512 MB: a probe that wrote 0x20400000, 0x40000000, 0x80000000 and 0xe0000000 in prom_init read its values back before the lock block and the old contents right after it, on CCA 0, 2 and 3 alike, while writes below 256 MB and every u-boot "mw" stuck. Since the cvmx bootmem free list keeps its nodes inside the free blocks themselves, the kernel's first split above 0x20000000 was lost, the walk of the free list stopped there, and the board came up with 248 MB of its 8 GB. Match the whole CN6XXX family, which is what these register accesses are keyed to. The CN63XX keeps exactly the same path. The geometry helpers in this file need the same treatment but not the same condition; they are handled in the next patch. Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/executive/cvmx-l2c.c | 22 ++++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c index 33b303691bc2..535efed7b1a2 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c @@ -54,7 +54,7 @@ int cvmx_l2c_get_core_way_partition(uint32_t core) if (core >= cvmx_octeon_num_cores()) return -1; - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff; /* @@ -91,14 +91,14 @@ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask) mask &= valid_mask; /* A UMSK setting which blocks all L2C Ways is an error on some chips */ - if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN6XXX)) return -1; /* Validate the core number */ if (core >= cvmx_octeon_num_cores()) return -1; - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask); return 0; } @@ -147,10 +147,10 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask) mask &= valid_mask; /* A UMSK setting which blocks all L2C Ways is an error on some chips */ - if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN6XXX)) return -1; - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask); else cvmx_write_csr(CVMX_L2C_SPAR4, @@ -160,7 +160,7 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask) int cvmx_l2c_get_hw_way_partition(void) { - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff; else return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF); @@ -313,7 +313,7 @@ static void fault_in(uint64_t addr, int len) int cvmx_l2c_lock_line(uint64_t addr) { - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { int shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT; uint64_t assoc = cvmx_l2c_get_num_assoc(); uint64_t tag = addr >> shift; @@ -460,7 +460,7 @@ void cvmx_l2c_flush(void) int cvmx_l2c_unlock_line(uint64_t address) { - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { int assoc; union cvmx_l2c_tag tag; uint32_t tag_addr; @@ -661,7 +661,7 @@ union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index) (int)index, cvmx_l2c_get_num_sets()); return tag; } - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { union cvmx_l2c_tadx_tag l2c_tadx_tag; uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) | @@ -745,7 +745,7 @@ uint32_t cvmx_l2c_address_to_index(uint64_t addr) } if (indxalias) { - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1< select the way of the cache block involved in From 2d1d4f443975acc64d81f0ededd44864542dbd08 Mon Sep 17 00:00:00 2001 From: Orgad Shaneh Date: Tue, 15 Sep 2026 07:12:45 +0000 Subject: [PATCH 06/30] MIPS: OCTEON: cvmx-l2c: add the CN66XX L2 geometry cvmx_l2c_get_set_bits() and cvmx_l2c_get_num_assoc() know the CN63XX as the only OCTEON II part, so on a CN6635 both fell through to their "Unsupported OCTEON Model" defaults: 2048 sets, and 8 ways which the CN3XXX/CN5XXX fuse path - a read of L2D_FUS3, which is not a register on OCTEON II - then shifted down to 2. The CN66XX L2 has the CN63XX geometry, 16 ways and 1024 sets, and reports its fused-off ways in MIO_FUS_DAT3[l2c_crip] like the rest of OCTEON II, so name it in those three branches. With this the board reports assoc 16, sets 1024, and cvmx_l2c_lock_line() computes the tag alias from the right associativity. The CN68XX and CN61XX are deliberately left alone: their L2 geometry differs from the CN63XX, and the CN68XX also uses bit <2> of MIO_FUS_DAT3[l2c_crip], which the decoding here does not handle. I have no such board to test on. Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/executive/cvmx-l2c.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c index 535efed7b1a2..373907e1e668 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c @@ -773,7 +773,9 @@ int cvmx_l2c_get_set_bits(void) if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) l2_set_bits = 11; /* 2048 sets */ - else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) + else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN66XX)) l2_set_bits = 10; /* 1024 sets */ else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) l2_set_bits = 9; /* 512 sets */ @@ -805,7 +807,8 @@ int cvmx_l2c_get_num_assoc(void) OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) l2_assoc = 8; - else if (OCTEON_IS_MODEL(OCTEON_CN63XX)) + else if (OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN66XX)) l2_assoc = 16; else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX)) @@ -816,7 +819,7 @@ int cvmx_l2c_get_num_assoc(void) } /* Check to see if part of the cache is disabled */ - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)) { union cvmx_mio_fus_dat3 mio_fus_dat3; mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); From 7d22c1e6d1fe6bda2270812f8ac2495499e6295a Mon Sep 17 00:00:00 2001 From: Orgad Shaneh Date: Tue, 15 Sep 2026 07:12:46 +0000 Subject: [PATCH 07/30] MIPS: OCTEON: read the L2 crippled fuses from MIO_FUS_DAT3 on OCTEON II prom_init() decides whether to lock lines into the L2 by reading L2D_FUS3, a CN3XXX/CN5XXX register. On OCTEON II the fuses that cripple the L2 are MIO_FUS_DAT3[l2c_crip] - which is what cvmx_l2c_get_num_assoc() already reads for those parts - so the test looks at an address that is not a register on the chip and gets a meaningless answer: it can skip L2 locking on a healthy cache, or lock into a reduced one. Pick the register by family in a small helper. Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/setup.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 1ad2602a0383..8938de9467ee 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -653,6 +653,24 @@ void octeon_user_io_init(void) write_c0_derraddr1(0); } +#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 +static bool __init octeon_l2_is_crippled(void) +{ + /* + * L2D_FUS3 exists on CN3XXX/CN5XXX only. On OCTEON II the + * crippled-L2 fuses live in MIO_FUS_DAT3[l2c_crip]. + */ + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + union cvmx_mio_fus_dat3 fus_dat3; + + fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); + return fus_dat3.s.l2c_crip != 0; + } + + return cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34); +} +#endif + /** * prom_init - Early entry point for arch setup */ @@ -801,7 +819,7 @@ void __init prom_init(void) } #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 - if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { + if (octeon_l2_is_crippled()) { pr_info("Skipping L2 locking due to reduced L2 cache size\n"); } else { uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; From bd978130307cfe330b98e7a5fccfd489d736f6a7 Mon Sep 17 00:00:00 2001 From: Orgad Shaneh Date: Tue, 15 Sep 2026 07:12:47 +0000 Subject: [PATCH 08/30] MIPS: OCTEON: program L2C_CTL, not L2C_CFG, on OCTEON II cvmx_helper_initialize_packet_io_global() sets the L2 arbitration modes by rewriting L2C_CFG. That register (0x1180080000000) does not exist on OCTEON II; there the L2 controller is configured through L2C_CTL (0x1180080800000), whose corresponding fields are rsp_arb_mode and xmc_arb_mode. On a CN6335 the stray write hung the board hard when this function ran - no exception, no watchdog, just a dead console. Keep the L2C_CFG write for CN3XXX/CN5XXX and program L2C_CTL on CN6XXX with the values the vendor SDK uses there (rsp_arb_mode 1, xmc_arb_mode 0), which is the same trade the existing code makes for the older parts: keep IO blocks from being starved under high L2 load. Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh Signed-off-by: Thomas Bogendoerfer --- .../cavium-octeon/executive/cvmx-helper.c | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c index 1985cd66806a..107b1be4a45e 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -1014,7 +1014,6 @@ int cvmx_helper_initialize_packet_io_global(void) { int result = 0; int interface; - union cvmx_l2c_cfg l2c_cfg; const int num_interfaces = cvmx_helper_get_number_of_interfaces(); /* @@ -1029,10 +1028,21 @@ int cvmx_helper_initialize_packet_io_global(void) * to the cores. This avoids conditions where IO blocks might * be starved under very high L2 loads. */ - l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); - l2c_cfg.s.lrf_arb_mode = 0; - l2c_cfg.s.rfb_arb_mode = 0; - cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64); + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + union cvmx_l2c_ctl l2c_ctl; + + l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL); + l2c_ctl.s.rsp_arb_mode = 1; + l2c_ctl.s.xmc_arb_mode = 0; + cvmx_write_csr(CVMX_L2C_CTL, l2c_ctl.u64); + } else { + union cvmx_l2c_cfg l2c_cfg; + + l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); + l2c_cfg.s.lrf_arb_mode = 0; + l2c_cfg.s.rfb_arb_mode = 0; + cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64); + } cvmx_pko_initialize_global(); for (interface = 0; interface < num_interfaces; interface++) { From 7b4b139612f8aa1bf85176740612baeea0b6c867 Mon Sep 17 00:00:00 2001 From: Orgad Shaneh Date: Tue, 15 Sep 2026 07:12:48 +0000 Subject: [PATCH 09/30] MIPS: OCTEON: require the Core-14449 workaround only on CN63XX pass 1 prom_free_prom_memory() probes the hint field of a compiler-emitted PREF and panics when it is not 28, which is what -Wa,-mfix-cn63xxp1 (CONFIG_CAVIUM_CN63XXP1) rewrites every prefetch in the kernel to. The test is gated on OCTEON_IS_MODEL(OCTEON_CN6XXX), so it fires on every OCTEON II part, including the pass 2 chips that do not need the workaround: Kernel panic - not syncing: OCTEON II DCache prefetch workaround not in place (cfa00004). Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1). on a CN6335-AAP pass 2.2. Core-14449 is a CN63XX pass 1.x erratum, and the vendor's own runtime check says so: it errors out only for OCTEON_CN63XX_PASS1_X without the fix, and otherwise merely warns about lost performance when fixed code runs on a part that is not a CN63XX. Narrow the check to CN63XX pass 1.x to match. The alternative - enabling CONFIG_CAVIUM_CN63XXP1 to satisfy the check - is not free: the assembler flag rewrites every prefetch in the kernel (77 of them in this build) to pref 0x1c, which is worth avoiding on an in-order core whose receive path is dominated by memcpy. uasm_i_pref() keeps its OCTEON_CN6XXX condition: it only touches the handful of runtime-generated TLB handlers, where the cost does not matter. Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 8938de9467ee..d2bba2fe636d 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -1127,7 +1127,7 @@ EXPORT_SYMBOL(prom_putchar); void __init prom_free_prom_memory(void) { - if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { /* Check for presence of Core-14449 fix. */ u32 insn; u32 *foo; From 975d4a6a6d4d23a39e2f49cafcc082d937960bc4 Mon Sep 17 00:00:00 2001 From: Orgad Shaneh Date: Tue, 15 Sep 2026 07:13:24 +0000 Subject: [PATCH 10/30] MIPS: mm: align hugetlb mappings in arch_get_unmapped_area() Since hugetlb mappings were made to go through the architecture's arch_get_unmapped_area{,_topdown}(), every architecture that implements those has to align hugetlb files itself. The generic implementation and loongarch do it with huge_page_mask_align(); MIPS was left out. A non-MAP_FIXED mmap() of a hugetlbfs file therefore returns an address that is only SHMLBA aligned, and the kernel then installs 2 MB PMDs for a VMA that starts in the middle of a PMD. The consequences on an Octeon (CN63XX) board running a process that links libhugetlbfs with HUGETLB_ELFMAP=R and HUGETLB_MORECORE=yes, all within a minute of start: the neighbouring 4 KB page table is clobbered, the TLB ends up with overlapping entries ("Caught Machine Check exception - caused by multiple matching entries in the TLB"), process exit trips BUG_ON(start & ~huge_page_mask(h)) in __unmap_hugepage_range(), and freed pages leak into unrelated kernel structures (oopses in the irq maple tree, in pte_offset_map, ...). Do what loongarch does in commit 3109d5ff484b ("LoongArch: Set hugetlb mmap base address aligned with pmd size"): when the file is a hugetlb file, use its page mask as the search alignment instead of the cache colour mask. Fixes: 7bd3f1e1a9ae ("mm: make hugetlb mappings go through mm_get_unmapped_area_vmflags") Cc: stable@vger.kernel.org # 6.13+ Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/mmap.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/mips/mm/mmap.c b/arch/mips/mm/mmap.c index 5d2a1225785b..119edaa928f3 100644 --- a/arch/mips/mm/mmap.c +++ b/arch/mips/mm/mmap.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -72,8 +73,11 @@ static unsigned long arch_get_unmapped_area_common(struct file *filp, } info.length = len; - info.align_mask = do_color_align ? (PAGE_MASK & shm_align_mask) : 0; info.align_offset = pgoff << PAGE_SHIFT; + if (filp && is_file_hugepages(filp)) + info.align_mask = huge_page_mask_align(filp); + else + info.align_mask = do_color_align ? (PAGE_MASK & shm_align_mask) : 0; if (dir == DOWN) { info.flags = VM_UNMAPPED_AREA_TOPDOWN; From 0cb17268887e1df5c425ea052f5146b42d126323 Mon Sep 17 00:00:00 2001 From: Orgad Shaneh Date: Tue, 15 Sep 2026 07:13:25 +0000 Subject: [PATCH 11/30] MIPS: mm: do not write a huge TLB entry when the probe misses __update_tlb() probes for the 8K pair at the address it is given and, for a huge pmd, writes the huge entry with tlbwi at the probed index or with tlbwr when the probe misses. That works only if the caller passes the faulting address, so that the probe finds the 4K entry the refill handler loaded for the faulting page and the huge entry replaces it. update_mmu_cache_pmd() is not called that way. do_set_pmd() has always passed the huge-aligned address, and since commit ebcfc63d6bca ("mm: abstract THP allocation") the anonymous THP fault path does too (map_anon_folio_pmd()). The probe then misses the stale 4K entry, which sits at the faulting page somewhere else in the 2 MB range, tlbwr adds a huge entry next to it, and the TLB holds two entries matching the faulting address. Octeon raises "Machine Check exception - caused by multiple matching entries in the TLB" on the next refill of that page; a process on a CN63XX board died this way within a second of start, on the first anonymous THP of its bss. Skip the write when the probe misses. The refill and TLBL/TLBS handlers probe the faulting address themselves and rewrite the stale entry with the huge one (they also set the software young bit), so the entry is installed on the next access at the cost of one exception. Fixes: fd062c847a8c ("MIPS: TLB support for hugetlbfs.") Cc: stable@vger.kernel.org Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/tlb-r4k.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 24fe85fa169d..78bafa317fa6 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -332,6 +332,19 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) /* this could be a huge page */ if (pmd_leaf(*pmdp)) { unsigned long lo; + + /* + * The probe above only covers the 8K pair at @address, and + * a huge mapping is installed with the huge-aligned address + * while the refill that started the fault left a 4K entry + * for the faulting page elsewhere in the range. Writing the + * huge entry to a random index would leave two entries + * matching the faulting address; leave it to the refill and + * TLBL/TLBS handlers, which probe the faulting address. + */ + if (idx < 0) + goto out; + write_c0_pagemask(PM_HUGE_MASK); ptep = (pte_t *)pmdp; lo = pte_to_entrylo(pte_val(*ptep)); @@ -339,10 +352,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) write_c0_entrylo1(lo + (HPAGE_SIZE >> 7)); mtc0_tlbw_hazard(); - if (idx < 0) - tlb_write_random(); - else - tlb_write_indexed(); + tlb_write_indexed(); tlbw_use_hazard(); write_c0_pagemask(PM_DEFAULT_MASK); } else @@ -380,6 +390,9 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) tlb_write_indexed(); } tlbw_use_hazard(); +#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT +out: +#endif htw_start(); flush_micro_tlb_vm(vma); From f1dd1f0c8d595a019be503d40060d25721313b4a Mon Sep 17 00:00:00 2001 From: Orgad Shaneh Date: Tue, 15 Sep 2026 08:18:24 +0000 Subject: [PATCH 12/30] MIPS: Octeon: size the swiotlb for a modular OHCI platform driver plat_swiotlb_setup() raises the swiotlb to 64 MB on OCTEON II with memory above 4 GB, because that OHCI can only DMA to 32 bits. The test is "#ifdef CONFIG_USB_OHCI_HCD_PLATFORM", which is false when the driver is a module - the usual way to build it - so the bump is silently skipped. What is left depends on the rest of the function: with PCI enabled the "memory past the BAR1 hole" branch happens to ask for the same 64 MB, but with CONFIG_PCI off - which is normal on these SoCs when no PCI devices are wired - swiotlbsize stays at the PAGE_SIZE it was initialised to. A full- or low-speed device on an OCTEON II board with more than 4 GB of RAM then has no bounce buffer to speak of. Use IS_ENABLED() so a modular OHCI gets the same sizing as a built-in one. Seen on a CN6635 board with 8 GB of RAM and CONFIG_USB_OHCI_HCD_PLATFORM=m. Fixes: a8667d706dfa ("MIPS: OCTEON: dma-octeon: fix OHCI USB config check") Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/dma-octeon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index 9fbba6a8fa4c..c049632fbcc3 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -228,7 +228,7 @@ void __init plat_swiotlb_setup(void) swiotlbsize = 64 * (1<<20); } #endif -#ifdef CONFIG_USB_OHCI_HCD_PLATFORM +#if IS_ENABLED(CONFIG_USB_OHCI_HCD_PLATFORM) /* OCTEON II ohci is only 32-bit. */ if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul) swiotlbsize = 64 * (1<<20); From 17b0e14d7bb155299c7702dfe81973052001cadb Mon Sep 17 00:00:00 2001 From: Orgad Shaneh Date: Tue, 15 Sep 2026 08:18:25 +0000 Subject: [PATCH 13/30] MIPS: Octeon: offer the RedBoot parser when it is modular The bootbus flash driver lists "RedBoot" among the partition parsers to try under "#ifdef CONFIG_MTD_REDBOOT_PARTS", so building that parser as a module drops it from the list and the partitions on such a chip are never found. Use IS_ENABLED(), like the USB device-tree fixups in octeon-platform.c. Untested - I have no board with RedBoot partitions; the change is by inspection, in the same family as the two above. Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/flash_setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c index 3395acde4d60..66d173b57c3f 100644 --- a/arch/mips/cavium-octeon/flash_setup.c +++ b/arch/mips/cavium-octeon/flash_setup.c @@ -22,7 +22,7 @@ static struct map_info flash_map; static struct mtd_info *mymtd; static const char *part_probe_types[] = { "cmdlinepart", -#ifdef CONFIG_MTD_REDBOOT_PARTS +#if IS_ENABLED(CONFIG_MTD_REDBOOT_PARTS) "RedBoot", #endif NULL From 199ddf893b63980ddf5c5de29f3b491d691c2967 Mon Sep 17 00:00:00 2001 From: Ethan Nelson-Moore Date: Thu, 17 Sep 2026 19:57:51 -0700 Subject: [PATCH 14/30] MIPS: remove unused header The last use of arch/mips/include/asm/amon.h was removed in commit 7fb6f7b0af67 ("MIPS: Remove deprecated CONFIG_MIPS_CMP"), but it was left behind. Remove it. Signed-off-by: Ethan Nelson-Moore Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/amon.h | 12 ------------ 1 file changed, 12 deletions(-) delete mode 100644 arch/mips/include/asm/amon.h diff --git a/arch/mips/include/asm/amon.h b/arch/mips/include/asm/amon.h deleted file mode 100644 index 3cc03c64a9c7..000000000000 --- a/arch/mips/include/asm/amon.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2013 Imagination Technologies Ltd. - * - * Arbitrary Monitor Support (AMON) - */ -int amon_cpu_avail(int cpu); -int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp, - unsigned long gp, unsigned long a0); From 997727638df92ea85821f8ee1b36c7ab1d2b6c76 Mon Sep 17 00:00:00 2001 From: Ethan Nelson-Moore Date: Thu, 17 Sep 2026 20:00:35 -0700 Subject: [PATCH 15/30] MIPS: remove unused header The last use of arch/mips/include/asm/mips-boards/sead3-addr.h was removed in commit 64601cb1343f ("leds: Remove SEAD-3 driver") but it was left behind. Remove it. Signed-off-by: Ethan Nelson-Moore Signed-off-by: Thomas Bogendoerfer --- .../mips/include/asm/mips-boards/sead3-addr.h | 83 ------------------- 1 file changed, 83 deletions(-) delete mode 100644 arch/mips/include/asm/mips-boards/sead3-addr.h diff --git a/arch/mips/include/asm/mips-boards/sead3-addr.h b/arch/mips/include/asm/mips-boards/sead3-addr.h deleted file mode 100644 index c0db57802f7c..000000000000 --- a/arch/mips/include/asm/mips-boards/sead3-addr.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2015 Imagination Technologies, Inc. - * written by Ralf Baechle - */ -#ifndef __ASM_MIPS_BOARDS_SEAD3_ADDR_H -#define __ASM_MIPS_BOARDS_SEAD3_ADDR_H - -/* - * Target #0 Register Decode - */ -#define SEAD3_SD_SPDCNF 0xbb000040 -#define SEAD3_SD_SPADDR 0xbb000048 -#define SEAD3_SD_DATA 0xbb000050 - -/* - * Target #1 Register Decode - */ -#define SEAD3_CFG 0xbb100110 -#define SEAD3_GIC_BASE_ADDRESS 0xbb1c0000 -#define SEAD3_SHARED_SECTION 0xbb1c0000 -#define SEAD3_VPE_LOCAL_SECTION 0xbb1c8000 -#define SEAD3_VPE_OTHER_SECTION 0xbb1cc000 -#define SEAD3_USER_MODE_VISIBLE_SECTION 0xbb1d0000 - -/* - * Target #3 Register Decode - */ -#define SEAD3_USB_HS_BASE 0xbb200000 -#define SEAD3_USB_HS_IDENTIFICATION_REGS 0xbb200000 -#define SEAD3_USB_HS_CAPABILITY_REGS 0xbb200100 -#define SEAD3_USB_HS_OPERATIONAL_REGS 0xbb200140 -#define SEAD3_RESERVED 0xbe800000 - -/* - * Target #3 Register Decode - */ -#define SEAD3_SRAM 0xbe000000 -#define SEAD3_OPTIONAL_SRAM 0xbe400000 -#define SEAD3_FPGA 0xbf000000 - -#define SEAD3_PI_PIC32_USB_STATUS 0xbf000060 -#define SEAD3_PI_PIC32_USB_STATUS_IO_RDY (1 << 0) -#define SEAD3_PI_PIC32_USB_STATUS_SPL_INT (1 << 1) -#define SEAD3_PI_PIC32_USB_STATUS_GPIOA_INT (1 << 2) -#define SEAD3_PI_PIC32_USB_STATUS_GPIOB_INT (1 << 3) - -#define SEAD3_PI_SOFT_ENDIAN 0xbf000070 - -#define SEAD3_CPLD_P_SWITCH 0xbf000200 -#define SEAD3_CPLD_F_SWITCH 0xbf000208 -#define SEAD3_CPLD_P_LED 0xbf000210 -#define SEAD3_CPLD_F_LED 0xbf000218 -#define SEAD3_NEWSC_LIVE 0xbf000220 -#define SEAD3_NEWSC_REG 0xbf000228 -#define SEAD3_NEWSC_CTRL 0xbf000230 - -#define SEAD3_LCD_CONTROL 0xbf000400 -#define SEAD3_LCD_DATA 0xbf000408 -#define SEAD3_CPLD_LCD_STATUS 0xbf000410 -#define SEAD3_CPLD_LCD_DATA 0xbf000418 - -#define SEAD3_CPLD_PI_DEVRST 0xbf000480 -#define SEAD3_CPLD_PI_DEVRST_IC32_RST (1 << 0) -#define SEAD3_RESERVED_0 0xbf000500 - -#define SEAD3_PIC32_REGISTERS 0xbf000600 -#define SEAD3_RESERVED_1 0xbf000700 -#define SEAD3_UART_CH_0 0xbf000800 -#define SEAD3_UART_CH_1 0xbf000900 -#define SEAD3_RESERVED_2 0xbf000a00 -#define SEAD3_ETHERNET 0xbf010000 -#define SEAD3_RESERVED_3 0xbf020000 -#define SEAD3_USER_EXPANSION 0xbf400000 -#define SEAD3_RESERVED_4 0xbf800000 -#define SEAD3_BOOT_FLASH_EXTENSION 0xbfa00000 -#define SEAD3_BOOT_FLASH 0xbfc00000 -#define SEAD3_REVISION_REGISTER 0xbfc00010 - -#endif /* __ASM_MIPS_BOARDS_SEAD3_ADDR_H */ From f5ef7769fe27e785ada13a740826068e9ca612bf Mon Sep 17 00:00:00 2001 From: Ethan Nelson-Moore Date: Thu, 17 Sep 2026 23:06:22 -0700 Subject: [PATCH 16/30] MIPS: remove unused header arch/mips/include/asm/cmp.h appears never to have been used by the kernel. CMP support was removed in commit 7fb6f7b0af67 ("MIPS: Remove deprecated CONFIG_MIPS_CMP"), but it was left behind. Remove it. Signed-off-by: Ethan Nelson-Moore Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/cmp.h | 10 ---------- 1 file changed, 10 deletions(-) delete mode 100644 arch/mips/include/asm/cmp.h diff --git a/arch/mips/include/asm/cmp.h b/arch/mips/include/asm/cmp.h deleted file mode 100644 index 71e20e6cd38d..000000000000 --- a/arch/mips/include/asm/cmp.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CMP_H -#define _ASM_CMP_H - -/* - * Definitions for CMP multitasking on MIPS cores - */ -struct task_struct; - -#endif /* _ASM_CMP_H */ From 7a8f286c235f5d308208cfdcb025b2a0e0c84742 Mon Sep 17 00:00:00 2001 From: WangYuli Date: Sat, 19 Sep 2026 16:14:13 +0100 Subject: [PATCH 17/30] MIPS: Only check -msym32 when need-compiler During 'make modules_install', the need-compiler variable is null, so Makefile.compiler isn't included. This results in call cc-option-yn returning nothing and consequently an error is issued: *** CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32. Stop. and the invocation terminated for configurations that set the Kconfig option named. Previously commit a79a404e6c22 ("MIPS: Fix CONFIG_CPU_DADDI_WORKAROUNDS `modules_install' regression") addressed the same issue for GCC versions now supported for Linux compilation, but caused a build error with Clang because it doesn't support '-msym32'. Then commit 18ca63a2e23c ("MIPS: Probe toolchain support of -msym32") fixed the issue with Clang, but reintroduced the 'make modules_install' error listed above. Wrap the handling of the '-msym32' option then with ifdef need-compiler, fixing said error for 'make modules_install'. For more technical details on why need-compiler is null during 'make modules_install' and why no compiler invocation is actually needed at this point, please refer to commit 4fe4a6374c4d ("MIPS: Only fiddle with CHECKFLAGS if need-compiler") and commit 805b2e1d427a ("kbuild: include Makefile.compiler only when compiler is needed"). NB leading 8 spaces rather than tabs required due to `make' syntax. Link: https://lore.kernel.org/all/alpine.DEB.2.21.2502120612000.65342@angie.orcam.me.uk/ Link: https://lore.kernel.org/all/alpine.DEB.2.21.2307180025120.62448@angie.orcam.me.uk/ Fixes: a79a404e6c22 ("MIPS: Fix CONFIG_CPU_DADDI_WORKAROUNDS `modules_install' regression") Reported-by: Maciej W. Rozycki Closes: https://lore.kernel.org/all/alpine.DEB.2.21.2501030535080.49841@angie.orcam.me.uk/ Co-developed-by: Chen Linxuan Signed-off-by: Chen Linxuan Signed-off-by: WangYuli Signed-off-by: Maciej W. Rozycki Reviewed-by: Chen Linxuan Signed-off-by: Thomas Bogendoerfer --- arch/mips/Makefile | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index cff1a9a43b89..3e9eb0650cac 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -290,18 +290,20 @@ drivers-$(CONFIG_PCI) += arch/mips/pci/ # We can always force a build with a 64-bits symbol format by # passing 'KBUILD_SYM32=no' option to the make's command line. # -ifdef CONFIG_64BIT - ifndef KBUILD_SYM32 - ifeq ($(shell expr $(load-y) \< 0xffffffff80000000), 0) - KBUILD_SYM32 = $(call cc-option-yn, -msym32) +ifdef need-compiler + ifdef CONFIG_64BIT + ifndef KBUILD_SYM32 + ifeq ($(shell expr $(load-y) \< 0xffffffff80000000), 0) + KBUILD_SYM32 = $(call cc-option-yn, -msym32) + endif endif - endif - ifeq ($(KBUILD_SYM32), y) - cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32 - else - ifeq ($(CONFIG_CPU_DADDI_WORKAROUNDS), y) - $(error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32) + ifeq ($(KBUILD_SYM32), y) + cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32 + else + ifeq ($(CONFIG_CPU_DADDI_WORKAROUNDS), y) + $(error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32) + endif endif endif endif From 271e680b17a40347cfc2d33f721249cbb82e34c8 Mon Sep 17 00:00:00 2001 From: WangYuli Date: Sat, 19 Sep 2026 16:14:20 +0100 Subject: [PATCH 18/30] MIPS: dec: Add missing inclusion to reset.h Pull the header directly that is required for `irqreturn_t' type. Fixes: 0eb77376912e ("MIPS: DEC: Fix prototypes for halt/reset handlers") Signed-off-by: WangYuli Signed-off-by: Maciej W. Rozycki Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/dec/reset.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/include/asm/dec/reset.h b/arch/mips/include/asm/dec/reset.h index 6af49f3f24da..caf60ef0edd0 100644 --- a/arch/mips/include/asm/dec/reset.h +++ b/arch/mips/include/asm/dec/reset.h @@ -10,6 +10,7 @@ #define __ASM_DEC_RESET_H #include +#include void __noreturn dec_machine_restart(char *command); void __noreturn dec_machine_halt(void); From 9109f3aa68e3d28a0250224d9323282dff0abccc Mon Sep 17 00:00:00 2001 From: WangYuli Date: Sat, 19 Sep 2026 16:14:36 +0100 Subject: [PATCH 19/30] MIPS: decstation_64_defconfig: Regenerate for 7.x Due to long-term changes in kernel build configurations, run 'make savedefconfig' to update the build configuration dependencies. This commit does not affect the actual .config file content, in preparation for future modifications to decstation_64_defconfig. Signed-off-by: WangYuli Signed-off-by: Maciej W. Rozycki Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/decstation_64_defconfig | 43 +++++++++-------------- 1 file changed, 16 insertions(+), 27 deletions(-) diff --git a/arch/mips/configs/decstation_64_defconfig b/arch/mips/configs/decstation_64_defconfig index 8afb8ac3ed78..7bbf51a401ed 100644 --- a/arch/mips/configs/decstation_64_defconfig +++ b/arch/mips/configs/decstation_64_defconfig @@ -1,27 +1,26 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_LOG_BUF_SHIFT=15 CONFIG_EXPERT=y # CONFIG_SGETMASK_SYSCALL is not set -# CONFIG_SYSFS_SYSCALL is not set -CONFIG_BPF_SYSCALL=y -# CONFIG_COMPAT_BRK is not set CONFIG_MACH_DECSTATION=y CONFIG_64BIT=y -CONFIG_PAGE_SIZE_16KB=y CONFIG_TC=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y # CONFIG_SUSPEND is not set +CONFIG_PAGE_SIZE_16KB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_PARTITION_ADVANCED=y CONFIG_OSF_PARTITION=y # CONFIG_EFI_PARTITION is not set +# CONFIG_COMPAT_BRK is not set CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_NET=y CONFIG_PACKET=y @@ -49,7 +48,6 @@ CONFIG_NETWORK_SECMARK=y CONFIG_IP_SCTP=m CONFIG_VLAN_8021Q=m # CONFIG_WIRELESS is not set -# CONFIG_UEVENT_HELPER is not set # CONFIG_FW_LOADER is not set # CONFIG_ALLOW_DEV_COREDUMP is not set CONFIG_MTD=m @@ -83,9 +81,9 @@ CONFIG_DECLANCE=y # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set # CONFIG_NET_VENDOR_ROCKER is not set @@ -114,13 +112,11 @@ CONFIG_FB_TGA=y CONFIG_FB_PMAG_AA=y CONFIG_FB_PMAG_BA=y CONFIG_FB_PMAGB_B=y -# CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE_COLUMNS=160 CONFIG_DUMMY_CONSOLE_ROWS=64 CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_LOGO_LINUX_CLUT224 is not set # CONFIG_HID is not set # CONFIG_USB_SUPPORT is not set @@ -168,31 +164,24 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=m CONFIG_CRYPTO_RSA=m -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_CHACHA20POLY1305=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_OFB=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_CMAC=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_CRC32=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_CRC32=m CONFIG_CRYPTO_LZO=m CONFIG_CRYPTO_842=m CONFIG_CRYPTO_LZ4=m From 4fdd071978eeb0d77948585c090192a833e0b007 Mon Sep 17 00:00:00 2001 From: WangYuli Date: Sat, 19 Sep 2026 16:14:41 +0100 Subject: [PATCH 20/30] MIPS: decstation_64_defconfig: Compile the kernel with warnings as errors All compilation issues with decstation_64_defconfig have been resolved, and it is safe to enable CONFIG_WERROR now. Signed-off-by: WangYuli Signed-off-by: Maciej W. Rozycki Reviewed-by: Maciej W. Rozycki Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/decstation_64_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/configs/decstation_64_defconfig b/arch/mips/configs/decstation_64_defconfig index 7bbf51a401ed..62efc81b394f 100644 --- a/arch/mips/configs/decstation_64_defconfig +++ b/arch/mips/configs/decstation_64_defconfig @@ -1,3 +1,4 @@ +CONFIG_WERROR=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_HIGH_RES_TIMERS=y From 0e1644296bf02d7f5d552ba97a74eeac908468fe Mon Sep 17 00:00:00 2001 From: WangYuli Date: Sat, 19 Sep 2026 16:14:46 +0100 Subject: [PATCH 21/30] MIPS: Eliminate redundant KBUILD_SYM32 check Given that KBUILD_SYM32=y is a prerequisite for this statement to be executed, it's logically redundant to verify KBUILD_SYM32 is y again. Signed-off-by: WangYuli Signed-off-by: Maciej W. Rozycki Signed-off-by: Thomas Bogendoerfer --- arch/mips/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 3e9eb0650cac..fad3d7974617 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -299,7 +299,7 @@ ifdef need-compiler endif ifeq ($(KBUILD_SYM32), y) - cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32 + cflags-y += -msym32 -DKBUILD_64BIT_SYM32 else ifeq ($(CONFIG_CPU_DADDI_WORKAROUNDS), y) $(error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32) From 02b040386885fd9a966996805b48ba7e9d93cd23 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Sat, 19 Sep 2026 16:14:55 +0100 Subject: [PATCH 22/30] MIPS: Reword KBUILD_SYM32 documentation for clarity It is currently hard to figure out what the inline documentation for the KBUILD_SYM32 option means as it speaks in generic build/ELF format terms which can mean just about anything, while the whole point of the option is whether kernel symbols can or cannot fit in the 32-bit value range. Adjust the description accordingly and also quote the more correct 'n' rather than 'no' setting (even though all that matters is whether it's 'y' or not). Signed-off-by: Maciej W. Rozycki Signed-off-by: Thomas Bogendoerfer --- arch/mips/Makefile | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index fad3d7974617..c84e5dbcb25c 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -285,10 +285,12 @@ cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ # -# Automatically detect the build format. By default we choose -# the elf format according to the load address. -# We can always force a build with a 64-bits symbol format by -# passing 'KBUILD_SYM32=no' option to the make's command line. +# Automatically detect whether to build a 64-bit kernel using symbols +# limited to 32-bit values, which produces more compact code. This +# relies on the kernel image being linked at a 32-bit load address, +# which we use to infer whether to use this arrangement for symbols. +# Use 'make KBUILD_SYM32=n' to override this default choice and force +# 64-bit symbols to be used instead. # ifdef need-compiler ifdef CONFIG_64BIT From fcc1517f7fdf71f9f5c567c5ae9ad3a39d7b375c Mon Sep 17 00:00:00 2001 From: WangYuli Date: Sat, 19 Sep 2026 16:15:02 +0100 Subject: [PATCH 23/30] MIPS: dec: Reorder header inclusions in setup.c Make the order alphabetic of headers included in setup.c. Signed-off-by: WangYuli Signed-off-by: Maciej W. Rozycki Signed-off-by: Thomas Bogendoerfer --- arch/mips/dec/setup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 78ad28ac16db..645473f4e098 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -18,16 +18,16 @@ #include #include #include +#include #include #include #include -#include #include #include -#include #include #include +#include #include #include #include From 26ec08290bbd777a6994f224272e463633413e2c Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 20 Sep 2026 20:20:47 -0700 Subject: [PATCH 24/30] docs: ABI: lefi: use literal blocks Use literal blocks for console I/O examples so that the lines aren't run together in the produced html. Signed-off-by: Randy Dunlap Signed-off-by: Thomas Bogendoerfer --- .../ABI/testing/sysfs-firmware-lefi-boardinfo | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo b/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo index 5e3f6148c52e..c4de1338db58 100644 --- a/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo +++ b/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo @@ -12,19 +12,19 @@ Description: requirement and specific for Loongson64, so only add a new boardinfo.c file in arch/mips/loongson64. - For example: + For example:: - [loongson@linux ~]$ cat /sys/firmware/lefi/boardinfo - Board Info - Manufacturer : LEMOTE - Board Name : LEMOTE-LS3A4000-7A1000-1w-V01-pc - Family : LOONGSON3 + [loongson@linux ~]$ cat /sys/firmware/lefi/boardinfo + Board Info + Manufacturer : LEMOTE + Board Name : LEMOTE-LS3A4000-7A1000-1w-V01-pc + Family : LOONGSON3 - BIOS Info - Vendor : Kunlun - Version : Kunlun-A1901-V4.1.3-20200414093938 - ROM Size : 4 KB - Release Date : 2020-04-14 + BIOS Info + Vendor : Kunlun + Version : Kunlun-A1901-V4.1.3-20200414093938 + ROM Size : 4 KB + Release Date : 2020-04-14 By the way, using dmidecode command can get the similar info if there exists SMBIOS in firmware, but the fact is that there is no SMBIOS on From 591639aba745abbcee24405525240b72b48e6757 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 20 Sep 2026 20:20:48 -0700 Subject: [PATCH 25/30] docs: ABI: lefi: drop "ROM Size" in sysfs file doc. The "ROM Size" line was dropped in a previous commit. Now delete it in the ABI documentation also. Fixes: bd2212d658d7 ("MIPS: Loongson64: remove ROM Size unit in boardinfo") Signed-off-by: Randy Dunlap Signed-off-by: Thomas Bogendoerfer --- Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo b/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo index c4de1338db58..abea10ace557 100644 --- a/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo +++ b/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo @@ -23,7 +23,6 @@ Description: BIOS Info Vendor : Kunlun Version : Kunlun-A1901-V4.1.3-20200414093938 - ROM Size : 4 KB Release Date : 2020-04-14 By the way, using dmidecode command can get the similar info if there From a799df8824dd0cb850b0775a6b8e0177d1c95fc2 Mon Sep 17 00:00:00 2001 From: Jeff Johnson Date: Tue, 22 Sep 2026 08:19:04 -0700 Subject: [PATCH 26/30] MIPS: generic: Remove undefined image 'ramdisk' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As originally reported by Guenter Roeck [1] and subsequently confirmed by me [2], a MIPS allmodconfig build can fail with: Error: configuration 'pcb110' references undefined image 'ramdisk' in property 'ramdisk' make[3]: *** [../arch/mips/boot/Makefile:173: arch/mips/boot/vmlinux.gz.itb] Error 1 make[2]: *** [../arch/mips/Makefile:403: vmlinux.gz.itb] Error 2 Or with: Error: configuration 'pcb105' references undefined image 'ramdisk' in property 'ramdisk' make[3]: *** [../arch/mips/boot/Makefile:173: arch/mips/boot/vmlinux.gz.itb] Error 1 make[2]: *** [../arch/mips/Makefile:403: vmlinux.gz.itb] Error 2 Guenter's original report made the observation that this was triggered by an operating system update since he saw the same errors appear on previously working kernels after the update. I prompted an LLM with the information available and it provided the following additional information: This is not a kernel bug — it's a mkimage behavior change in u-boot-tools. Your system recently received an upgrade from u-boot-tools 2024.01 => 2025.10 (Ubuntu 24.04 noble-security), which included two upstream commits from June 2025: - tools: mkimage: validate image references in FIT configurations (commit 7a8b25a) - tools: mkimage: propagate error codes from fit_handle_file() (commit 21705d3) These commits made mkimage strictly validate that every image name referenced in a configurations node actually exists in the images section. Previously it silently ignored undefined references, now it errors out. The offending files in the kernel are arch/mips/generic/board-jaguar2.its.S and arch/mips/generic/board-serval.its.S — their configurations reference ramdisk = "ramdisk" but no ramdisk image node is ever defined anywhere in the FIT source. This was always technically wrong; the new u-boot-tools 2025.10 just enforces it. To fix the issue, remove the stale ramdisk references from both ITS files. Assisted-by: LLM Reported-by: Guenter Roeck Link: https://lore.kernel.org/all/f817c158-412b-4fd1-9941-9c2ff421b91a@roeck-us.net/ # [1] Reported-by: Jeff Johnson Link: https://lore.kernel.org/all/7eca1c7f-52d5-43bc-afcb-1f6ac198e391@oss.qualcomm.com/ # [2] Signed-off-by: Jeff Johnson Tested-by: Guenter Roeck Signed-off-by: Thomas Bogendoerfer --- arch/mips/generic/board-jaguar2.its.S | 2 -- arch/mips/generic/board-serval.its.S | 1 - 2 files changed, 3 deletions(-) diff --git a/arch/mips/generic/board-jaguar2.its.S b/arch/mips/generic/board-jaguar2.its.S index c2b8d479b26c..a91a06f1254f 100644 --- a/arch/mips/generic/board-jaguar2.its.S +++ b/arch/mips/generic/board-jaguar2.its.S @@ -28,13 +28,11 @@ description = "Jaguar2 Linux kernel"; kernel = "kernel"; fdt = "fdt-jaguar2_pcb110"; - ramdisk = "ramdisk"; }; pcb111 { description = "Jaguar2 Linux kernel"; kernel = "kernel"; fdt = "fdt-jaguar2_pcb111"; - ramdisk = "ramdisk"; }; }; }; diff --git a/arch/mips/generic/board-serval.its.S b/arch/mips/generic/board-serval.its.S index dde833efe980..3b89e208d29a 100644 --- a/arch/mips/generic/board-serval.its.S +++ b/arch/mips/generic/board-serval.its.S @@ -18,7 +18,6 @@ description = "Serval Linux kernel"; kernel = "kernel"; fdt = "fdt-serval_pcb105"; - ramdisk = "ramdisk"; }; }; }; From f552e14f77bfce3e7ee0bb268ab023951baec3ff Mon Sep 17 00:00:00 2001 From: Udaya Kiran Challa Date: Fri, 31 Jul 2026 23:17:51 +0530 Subject: [PATCH 27/30] mips: dts: pic32: pic32mzda: Remove unused address-cells, size-cells property The #address-cells and #size-cells properties are not strictly needed since the child nodes don't have reg properties Suggested-by: Rob Herring Signed-off-by: Udaya Kiran Challa Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/pic32/pic32mzda.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/mips/boot/dts/pic32/pic32mzda.dtsi b/arch/mips/boot/dts/pic32/pic32mzda.dtsi index feca35ba56a4..433dff3cf14f 100644 --- a/arch/mips/boot/dts/pic32/pic32mzda.dtsi +++ b/arch/mips/boot/dts/pic32/pic32mzda.dtsi @@ -76,8 +76,6 @@ evic: interrupt-controller@1f810000 { }; pic32_pinctrl: pinctrl@1f801400 { - #address-cells = <1>; - #size-cells = <1>; compatible = "microchip,pic32mzda-pinctrl"; reg = <0x1f801400 0x400>; clocks = <&rootclk PB1CLK>; From 3a07f4b33f44c0a433a26fdeb7235b97430d2e8a Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Thu, 1 Oct 2026 05:30:15 +0000 Subject: [PATCH 28/30] MIPS: GT64120: Remove duplicate GT_PCI1M1LD_OFS and GT_PCI1M1HD_OFS The GT_PCI1M1LD_OFS and GT_PCI1M1HD_OFS register offsets are defined twice in a row with identical values. Identical macro redefinitions are valid C, so the compiler never warned about it. Drop the second copy. No functional change. Signed-off-by: Aristo Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/gt64120.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h index 5d68d726598a..2ad770ff3c56 100644 --- a/arch/mips/include/asm/gt64120.h +++ b/arch/mips/include/asm/gt64120.h @@ -45,8 +45,6 @@ #define GT_PCI1M0HD_OFS 0x0a8 #define GT_PCI1M1LD_OFS 0x0b0 #define GT_PCI1M1HD_OFS 0x0b8 -#define GT_PCI1M1LD_OFS 0x0b0 -#define GT_PCI1M1HD_OFS 0x0b8 #define GT_SCS10AR_OFS 0x0d0 #define GT_SCS32AR_OFS 0x0d8 From 2cc5829e316d54a485c786ccd2f11e05215e62b3 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Sun, 27 Sep 2026 11:15:10 +0200 Subject: [PATCH 29/30] MIPS: octeon: Use MIPS_MACHINE for boards without provided device tree There are older Octeon boards with ld U-Boots, which don't use and pass a device tree to the kernel. Use MIPS_MACHINE mechanism to get a device tree. Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/setup.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index d2bba2fe636d..7497be7b9431 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include @@ -1159,7 +1160,7 @@ void __init octeon_fill_mac_addresses(void); void __init device_tree_init(void) { - const void *fdt; + const void *fdt = NULL; bool do_prune; bool fill_mac; @@ -1178,12 +1179,28 @@ void __init device_tree_init(void) do_prune = false; fill_mac = false; pr_info("Using passed Device Tree.\n"); - } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { - fdt = &__dtb_octeon_68xx_begin; - do_prune = true; - fill_mac = true; } else { - fdt = &__dtb_octeon_3xxx_begin; + const struct mips_machine *check_mach; + + for_each_mips_machine(check_mach) { + if (!check_mach->detect) + continue; + if (!check_mach->detect()) + continue; + + fdt = check_mach->fdt; + do_prune = false; + fill_mac = true; + pr_info("Using compiled-in Device Tree.\n"); + break; + } + } + + if (!fdt) { + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + fdt = &__dtb_octeon_68xx_begin; + else + fdt = &__dtb_octeon_3xxx_begin; do_prune = true; fill_mac = true; } From bfe97f12a0a64c3682be21a02404238e3b91e945 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Sun, 27 Sep 2026 11:15:11 +0200 Subject: [PATCH 30/30] MIPS: octeon: Add detection of UBNT Edgeroute Lite devices The U-Boot of Ubiquiti Edgerouter Lite don't provide a DT to the kernel. Use MIPS_MACHINE mechanism to provide one. Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/cavium-octeon/Makefile | 1 + arch/mips/cavium-octeon/Kconfig | 5 +++++ arch/mips/cavium-octeon/Makefile | 2 ++ arch/mips/cavium-octeon/board-ubnt.c | 16 ++++++++++++++++ 4 files changed, 24 insertions(+) create mode 100644 arch/mips/cavium-octeon/board-ubnt.c diff --git a/arch/mips/boot/dts/cavium-octeon/Makefile b/arch/mips/boot/dts/cavium-octeon/Makefile index 48085bca666c..aa3a5ff1468d 100644 --- a/arch/mips/boot/dts/cavium-octeon/Makefile +++ b/arch/mips/boot/dts/cavium-octeon/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb +dtb-$(CONFIG_OCTEON_BOARD_UBNT) += ubnt_e100.dtb diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 450e979ef5d9..f3618117cc39 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -89,4 +89,9 @@ config OCTEON_ILM To compile this driver as a module, choose M here. The module will be called octeon-ilm +config OCTEON_BOARD_UBNT + bool "Support Ubiquiti Devices" + help + Enable this for missing Ubiquit device trees and quirks + endif # CAVIUM_OCTEON_SOC diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index ab84ede0cbe0..c9b52c94a8ca 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -18,3 +18,5 @@ obj-y += executive/ obj-$(CONFIG_MTD) += flash_setup.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o + +obj-$(CONFIG_OCTEON_BOARD_UBNT) += board-ubnt.o diff --git a/arch/mips/cavium-octeon/board-ubnt.c b/arch/mips/cavium-octeon/board-ubnt.c new file mode 100644 index 000000000000..e89ab3a02f49 --- /dev/null +++ b/arch/mips/cavium-octeon/board-ubnt.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include + +static __init bool ubnt_e100_detect(void) +{ + return cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E100; +} + +extern const char __dtb_ubnt_e100_begin[]; + +MIPS_MACHINE(ubnt_e100) = { + .fdt = __dtb_ubnt_e100_begin, + .detect = ubnt_e100_detect, +};