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drm/msm/dsi/phy: Add support for Kaanapali

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Add DSI PHY support for the Kaanapali platform, Kaanapali introduce
addition of DSI2/DSI2_phy compared to SM8650. However, based on the
HPG diagram, only DSI0_phy and DSI1_phy works.

Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/698705/
Link: https://lore.kernel.org/r/20260115092749.533-7-yuanjie.yang@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Yuanjie Yang 2026-01-15 17:27:43 +08:00 committed by Dmitry Baryshkov
parent 3d2d7a3386
commit 223bff623c
3 changed files with 26 additions and 0 deletions
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2
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
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@ -577,6 +577,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_4nm_8650_cfgs },
{ .compatible = "qcom,sm8750-dsi-phy-3nm",
.data = &dsi_phy_3nm_8750_cfgs },
{ .compatible = "qcom,kaanapali-dsi-phy-3nm",
.data = &dsi_phy_3nm_kaanapali_cfgs },
#endif
{}
};

1
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
View File

@ -64,6 +64,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs;
struct msm_dsi_dphy_timing {
u32 clk_zero;

23
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
View File

@ -1504,3 +1504,26 @@ const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = {
.num_dsi_phy = 2,
.quirks = DSI_PHY_7NM_QUIRK_V7_0,
};
const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs = {
.has_phy_lane = true,
.regulator_data = dsi_phy_7nm_98000uA_regulators,
.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
.ops = {
.enable = dsi_7nm_phy_enable,
.disable = dsi_7nm_phy_disable,
.pll_init = dsi_pll_7nm_init,
.save_pll_state = dsi_7nm_pll_save_state,
.restore_pll_state = dsi_7nm_pll_restore_state,
.set_continuous_clock = dsi_7nm_set_continuous_clock,
},
.min_pll_rate = 600000000UL,
#ifdef CONFIG_64BIT
.max_pll_rate = 5000000000UL,
#else
.max_pll_rate = ULONG_MAX,
#endif
.io_start = { 0x9ac1000, 0x9ac4000 },
.num_dsi_phy = 2,
.quirks = DSI_PHY_7NM_QUIRK_V7_0,
};