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net/mlx5: Resource tables, Use async events chain
Remove the explicit call to QP/SRQ resources events handlers on several FW events and let resources logic register resources events notifiers via the new API. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Saeed Mahameed
parent
71edc69ca1
commit
221c14f3d1
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@ -324,7 +324,6 @@ static irqreturn_t mlx5_eq_async_int(int irq, void *eq_ptr)
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struct mlx5_eqe *eqe;
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int set_ci = 0;
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u32 cqn = -1;
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u32 rsn;
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u8 port;
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dev = eq->dev;
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@ -340,34 +339,6 @@ static irqreturn_t mlx5_eq_async_int(int irq, void *eq_ptr)
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mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
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eq->eqn, eqe_type_str(eqe->type));
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switch (eqe->type) {
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case MLX5_EVENT_TYPE_DCT_DRAINED:
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rsn = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff;
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rsn |= (MLX5_RES_DCT << MLX5_USER_INDEX_LEN);
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mlx5_rsc_event(dev, rsn, eqe->type);
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break;
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case MLX5_EVENT_TYPE_PATH_MIG:
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case MLX5_EVENT_TYPE_COMM_EST:
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case MLX5_EVENT_TYPE_SQ_DRAINED:
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case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
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case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
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case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
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case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
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case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
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rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
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rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
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mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
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eqe_type_str(eqe->type), eqe->type, rsn);
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mlx5_rsc_event(dev, rsn, eqe->type);
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break;
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case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
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case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
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rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
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mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
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eqe_type_str(eqe->type), eqe->type, rsn);
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mlx5_srq_event(dev, rsn, eqe->type);
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break;
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case MLX5_EVENT_TYPE_PORT_CHANGE:
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port = (eqe->data.port.port >> 4) & 0xf;
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switch (eqe->sub_type) {
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@ -38,11 +38,11 @@
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#include <linux/mlx5/transobj.h>
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#include "mlx5_core.h"
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#include "lib/eq.h"
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static struct mlx5_core_rsc_common *mlx5_get_rsc(struct mlx5_core_dev *dev,
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u32 rsn)
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static struct mlx5_core_rsc_common *
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mlx5_get_rsc(struct mlx5_qp_table *table, u32 rsn)
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{
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struct mlx5_qp_table *table = &dev->priv.qp_table;
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struct mlx5_core_rsc_common *common;
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spin_lock(&table->lock);
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@ -53,11 +53,6 @@ static struct mlx5_core_rsc_common *mlx5_get_rsc(struct mlx5_core_dev *dev,
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spin_unlock(&table->lock);
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if (!common) {
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mlx5_core_warn(dev, "Async event for bogus resource 0x%x\n",
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rsn);
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return NULL;
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}
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return common;
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}
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@ -120,14 +115,52 @@ static bool is_event_type_allowed(int rsc_type, int event_type)
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}
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}
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void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
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static int rsc_event_notifier(struct notifier_block *nb,
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unsigned long type, void *data)
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{
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struct mlx5_core_rsc_common *common = mlx5_get_rsc(dev, rsn);
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struct mlx5_core_rsc_common *common;
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struct mlx5_qp_table *table;
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struct mlx5_core_dev *dev;
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struct mlx5_core_dct *dct;
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u8 event_type = (u8)type;
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struct mlx5_core_qp *qp;
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struct mlx5_priv *priv;
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struct mlx5_eqe *eqe;
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u32 rsn;
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if (!common)
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return;
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switch (event_type) {
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case MLX5_EVENT_TYPE_DCT_DRAINED:
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eqe = data;
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rsn = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff;
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rsn |= (MLX5_RES_DCT << MLX5_USER_INDEX_LEN);
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break;
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case MLX5_EVENT_TYPE_PATH_MIG:
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case MLX5_EVENT_TYPE_COMM_EST:
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case MLX5_EVENT_TYPE_SQ_DRAINED:
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case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
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case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
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case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
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case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
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case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
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eqe = data;
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rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
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rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
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break;
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default:
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return NOTIFY_DONE;
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}
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table = mlx5_nb_cof(nb, struct mlx5_qp_table, nb);
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priv = container_of(table, struct mlx5_priv, qp_table);
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dev = container_of(priv, struct mlx5_core_dev, priv);
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mlx5_core_dbg(dev, "event (%d) arrived on resource 0x%x\n", eqe->type, rsn);
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common = mlx5_get_rsc(table, rsn);
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if (!common) {
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mlx5_core_warn(dev, "Async event for bogus resource 0x%x\n", rsn);
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return NOTIFY_OK;
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}
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if (!is_event_type_allowed((rsn >> MLX5_USER_INDEX_LEN), event_type)) {
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mlx5_core_warn(dev, "event 0x%.2x is not allowed on resource 0x%.8x\n",
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@ -152,6 +185,8 @@ void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
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}
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out:
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mlx5_core_put_rsc(common);
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return NOTIFY_OK;
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}
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static int create_resource_common(struct mlx5_core_dev *dev,
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@ -487,10 +522,16 @@ void mlx5_init_qp_table(struct mlx5_core_dev *dev)
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spin_lock_init(&table->lock);
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INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
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mlx5_qp_debugfs_init(dev);
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MLX5_NB_INIT(&table->nb, rsc_event_notifier, NOTIFY_ANY);
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mlx5_eq_notifier_register(dev, &table->nb);
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}
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void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev)
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{
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struct mlx5_qp_table *table = &dev->priv.qp_table;
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mlx5_eq_notifier_unregister(dev, &table->nb);
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mlx5_qp_debugfs_cleanup(dev);
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}
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@ -676,8 +717,9 @@ struct mlx5_core_rsc_common *mlx5_core_res_hold(struct mlx5_core_dev *dev,
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enum mlx5_res_type res_type)
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{
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u32 rsn = res_num | (res_type << MLX5_USER_INDEX_LEN);
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struct mlx5_qp_table *table = &dev->priv.qp_table;
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return mlx5_get_rsc(dev, rsn);
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return mlx5_get_rsc(table, rsn);
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}
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EXPORT_SYMBOL_GPL(mlx5_core_res_hold);
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@ -36,13 +36,25 @@
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#include <linux/mlx5/cmd.h>
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#include <linux/mlx5/srq.h>
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#include <rdma/ib_verbs.h>
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#include "mlx5_core.h"
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#include <linux/mlx5/transobj.h>
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#include "mlx5_core.h"
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#include "lib/eq.h"
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void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type)
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static int srq_event_notifier(struct mlx5_srq_table *table,
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unsigned long type, void *data)
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{
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struct mlx5_srq_table *table = &dev->priv.srq_table;
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struct mlx5_core_dev *dev;
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struct mlx5_core_srq *srq;
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struct mlx5_priv *priv;
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struct mlx5_eqe *eqe;
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u32 srqn;
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priv = container_of(table, struct mlx5_priv, srq_table);
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dev = container_of(priv, struct mlx5_core_dev, priv);
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eqe = data;
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srqn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
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mlx5_core_dbg(dev, "SRQ event (%d): srqn 0x%x\n", eqe->type, srqn);
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spin_lock(&table->lock);
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@ -54,13 +66,35 @@ void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type)
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if (!srq) {
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mlx5_core_warn(dev, "Async event for bogus SRQ 0x%08x\n", srqn);
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return;
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return NOTIFY_OK;
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}
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srq->event(srq, event_type);
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srq->event(srq, eqe->type);
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if (atomic_dec_and_test(&srq->refcount))
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complete(&srq->free);
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return NOTIFY_OK;
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}
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static int catas_err_notifier(struct notifier_block *nb,
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unsigned long type, void *data)
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{
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struct mlx5_srq_table *table;
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table = mlx5_nb_cof(nb, struct mlx5_srq_table, catas_err_nb);
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/* type == MLX5_EVENT_TYPE_SRQ_CATAS_ERROR */
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return srq_event_notifier(table, type, data);
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}
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static int rq_limit_notifier(struct notifier_block *nb,
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unsigned long type, void *data)
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{
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struct mlx5_srq_table *table;
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table = mlx5_nb_cof(nb, struct mlx5_srq_table, rq_limit_nb);
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/* type == MLX5_EVENT_TYPE_SRQ_RQ_LIMIT */
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return srq_event_notifier(table, type, data);
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}
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static int get_pas_size(struct mlx5_srq_attr *in)
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@ -708,9 +742,18 @@ void mlx5_init_srq_table(struct mlx5_core_dev *dev)
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memset(table, 0, sizeof(*table));
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spin_lock_init(&table->lock);
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INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
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MLX5_NB_INIT(&table->catas_err_nb, catas_err_notifier, SRQ_CATAS_ERROR);
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mlx5_eq_notifier_register(dev, &table->catas_err_nb);
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MLX5_NB_INIT(&table->rq_limit_nb, rq_limit_notifier, SRQ_RQ_LIMIT);
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mlx5_eq_notifier_register(dev, &table->rq_limit_nb);
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}
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void mlx5_cleanup_srq_table(struct mlx5_core_dev *dev)
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{
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/* nothing */
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struct mlx5_srq_table *table = &dev->priv.srq_table;
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mlx5_eq_notifier_unregister(dev, &table->rq_limit_nb);
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mlx5_eq_notifier_unregister(dev, &table->catas_err_nb);
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}
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@ -464,6 +464,8 @@ struct mlx5_core_health {
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};
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struct mlx5_qp_table {
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struct mlx5_nb nb;
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/* protect radix tree
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*/
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spinlock_t lock;
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@ -471,6 +473,8 @@ struct mlx5_qp_table {
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};
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struct mlx5_srq_table {
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struct mlx5_nb catas_err_nb;
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struct mlx5_nb rq_limit_nb;
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/* protect radix tree
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*/
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spinlock_t lock;
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@ -978,8 +982,6 @@ void mlx5_unregister_debugfs(void);
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void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
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void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
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void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
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void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
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struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
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int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
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unsigned int *irqn);
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