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drm/amd/display: Program pixclk according to dcn revision

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[WHY&HOW]
Pixel clock programming should be built per dcn revision, not hardcoded to use
dcn20.

Reviewed-by: Chris Park <chris.park@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone 2024-02-28 21:05:21 -05:00 committed by Alex Deucher
parent 5b53390e4b
commit 22194e71ea
1 changed files with 6 additions and 1 deletions
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7
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
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@ -1282,8 +1282,13 @@ void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
{
struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;
dcn20_build_pipe_pix_clk_params(pipe_ctx);
if (pool->funcs->build_pipe_pix_clk_params) {
pool->funcs->build_pipe_pix_clk_params(pipe_ctx);
} else {
dcn20_build_pipe_pix_clk_params(pipe_ctx);
}
pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;