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arm64: RSI: fix field-spanning write warning in attestation token init
The challenge is passed in registers a1 through a8. However, copying to
®s.a1 makes FORTIFY treat the destination as the single a1 field,
resulting in a field-spanning write warning. [1]
Overlay the SMCCC register structure with an RSI-specific argument
layout and copy the challenge into an explicit 64-byte array. This keeps
the existing a1-a8 argument encoding while giving the copy a correctly
sized destination object.
[1]
memcpy: detected field-spanning write (size 64) of single field "®s.a1" at ./arch/arm64/include/asm/rsi_cmds.h:119 (size 8)
WARNING: ./arch/arm64/include/asm/rsi_cmds.h:119 at rsi_attestation_token_init+0xdc/0xf8 [arm_cca_guest], CPU#0: cat/3314
Fixes: b880a80011 ("arm64: rsi: Add RSI definitions")
Signed-off-by: Kohei Enju <enju.kohei@fujitsu.com>
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
parent
ecc2e04686
commit
221049874b
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@ -88,6 +88,14 @@ static inline long rsi_set_addr_range_state(phys_addr_t start,
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return res.a0;
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}
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#define RSI_ATTEST_CHALLENGE_MIN_SIZE 32
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#define RSI_ATTEST_CHALLENGE_MAX_SIZE 64
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struct rsi_attestation_token_init_args {
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unsigned long fid;
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u8 challenge[RSI_ATTEST_CHALLENGE_MAX_SIZE];
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};
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/**
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* rsi_attestation_token_init - Initialise the operation to retrieve an
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* attestation token.
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@ -109,18 +117,21 @@ static inline long rsi_set_addr_range_state(phys_addr_t start,
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static inline long
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rsi_attestation_token_init(const u8 *challenge, unsigned long size)
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{
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struct arm_smccc_1_2_regs regs = { 0 };
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union {
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struct arm_smccc_1_2_regs regs;
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struct rsi_attestation_token_init_args init;
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} args = { 0 };
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/* The challenge must be at least 32bytes and at most 64bytes */
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if (!challenge || size < 32 || size > 64)
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if (!challenge || size < RSI_ATTEST_CHALLENGE_MIN_SIZE ||
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size > RSI_ATTEST_CHALLENGE_MAX_SIZE)
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return -EINVAL;
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regs.a0 = SMC_RSI_ATTESTATION_TOKEN_INIT;
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memcpy(®s.a1, challenge, size);
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arm_smccc_1_2_smc(®s, ®s);
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args.init.fid = SMC_RSI_ATTESTATION_TOKEN_INIT;
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memcpy(args.init.challenge, challenge, size);
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arm_smccc_1_2_smc(&args.regs, &args.regs);
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if (regs.a0 == RSI_SUCCESS)
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return regs.a1;
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if (args.regs.a0 == RSI_SUCCESS)
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return args.regs.a1;
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return -EINVAL;
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}
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