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net: dsa: vsc73xx: convert to PHYLINK
This patch replaces the adjust_link api with the phylink apis that provide equivalent functionality. The remaining functionality from the adjust_link is now covered in the mac_link_* and mac_config from phylink_mac_ops structure. Removes: .adjust_link Adds phylink_mac_ops structure: .mac_config .mac_link_up .mac_link_down Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> Link: https://lore.kernel.org/r/20240417205048.3542839-3-paweldembicki@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Pawel Dembicki
Jakub Kicinski
parent
eb7e33d01d
commit
21fc3416ea
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@ -717,16 +717,111 @@ static void vsc73xx_init_port(struct vsc73xx *vsc, int port)
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port, VSC73XX_C_RX0, 0);
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}
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static void vsc73xx_adjust_enable_port(struct vsc73xx *vsc,
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int port, struct phy_device *phydev,
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u32 initval)
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static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval)
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{
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u32 val = initval;
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int ret, err;
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u32 val;
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/* Disable RX on this port */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
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VSC73XX_MAC_CFG,
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VSC73XX_MAC_CFG_RX_EN, 0);
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/* Discard packets */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
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VSC73XX_ARBDISC, BIT(port), BIT(port));
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/* Wait until queue is empty */
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ret = read_poll_timeout(vsc73xx_read, err,
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err < 0 || (val & BIT(port)),
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VSC73XX_POLL_SLEEP_US,
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VSC73XX_POLL_TIMEOUT_US, false,
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vsc, VSC73XX_BLOCK_ARBITER, 0,
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VSC73XX_ARBEMPTY, &val);
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if (ret)
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dev_err(vsc->dev,
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"timeout waiting for block arbiter\n");
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else if (err < 0)
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dev_err(vsc->dev, "error reading arbiter\n");
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/* Put this port into reset */
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vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG,
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VSC73XX_MAC_CFG_RESET | initval);
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}
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static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode,
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const struct phylink_link_state *state)
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{
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struct dsa_port *dp = dsa_phylink_to_port(config);
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struct vsc73xx *vsc = dp->ds->priv;
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int port = dp->index;
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/* Special handling of the CPU-facing port */
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if (port == CPU_PORT) {
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/* Other ports are already initialized but not this one */
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vsc73xx_init_port(vsc, CPU_PORT);
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/* Select the external port for this interface (EXT_PORT)
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* Enable the GMII GTX external clock
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* Use double data rate (DDR mode)
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*/
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vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
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CPU_PORT,
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VSC73XX_ADVPORTM,
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VSC73XX_ADVPORTM_EXT_PORT |
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VSC73XX_ADVPORTM_ENA_GTX |
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VSC73XX_ADVPORTM_DDR_MODE);
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}
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}
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static void vsc73xx_mac_link_down(struct phylink_config *config,
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unsigned int mode, phy_interface_t interface)
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{
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struct dsa_port *dp = dsa_phylink_to_port(config);
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struct vsc73xx *vsc = dp->ds->priv;
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int port = dp->index;
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/* This routine is described in the datasheet (below ARBDISC register
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* description)
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*/
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vsc73xx_reset_port(vsc, port, 0);
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/* Allow backward dropping of frames from this port */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
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VSC73XX_SBACKWDROP, BIT(port), BIT(port));
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/* Receive mask (disable forwarding) */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
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VSC73XX_RECVMASK, BIT(port), 0);
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}
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static void vsc73xx_mac_link_up(struct phylink_config *config,
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struct phy_device *phy, unsigned int mode,
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phy_interface_t interface, int speed,
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int duplex, bool tx_pause, bool rx_pause)
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{
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struct dsa_port *dp = dsa_phylink_to_port(config);
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struct vsc73xx *vsc = dp->ds->priv;
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int port = dp->index;
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u32 val;
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u8 seed;
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/* Reset this port FIXME: break out subroutine */
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val |= VSC73XX_MAC_CFG_RESET;
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vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val);
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if (speed == SPEED_1000)
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val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M;
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else
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val = VSC73XX_MAC_CFG_TX_IPG_100_10M;
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if (interface == PHY_INTERFACE_MODE_RGMII)
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val |= VSC73XX_MAC_CFG_CLK_SEL_1000M;
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else
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val |= VSC73XX_MAC_CFG_CLK_SEL_EXT;
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if (duplex == DUPLEX_FULL)
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val |= VSC73XX_MAC_CFG_FDX;
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/* This routine is described in the datasheet (below ARBDISC register
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* description)
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*/
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vsc73xx_reset_port(vsc, port, val);
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/* Seed the port randomness with randomness */
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get_random_bytes(&seed, 1);
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@ -745,6 +840,14 @@ static void vsc73xx_adjust_enable_port(struct vsc73xx *vsc,
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VSC73XX_FCCONF_FLOW_CTRL_OBEY |
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0xff);
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/* Accept packets again */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
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VSC73XX_ARBDISC, BIT(port), 0);
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/* Enable port (forwarding) in the receive mask */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
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VSC73XX_RECVMASK, BIT(port), BIT(port));
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/* Disallow backward dropping of frames from this port */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
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VSC73XX_SBACKWDROP, BIT(port), 0);
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@ -757,125 +860,6 @@ static void vsc73xx_adjust_enable_port(struct vsc73xx *vsc,
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VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN);
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}
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static void vsc73xx_adjust_link(struct dsa_switch *ds, int port,
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struct phy_device *phydev)
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{
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struct vsc73xx *vsc = ds->priv;
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u32 val;
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/* Special handling of the CPU-facing port */
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if (port == CPU_PORT) {
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/* Other ports are already initialized but not this one */
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vsc73xx_init_port(vsc, CPU_PORT);
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/* Select the external port for this interface (EXT_PORT)
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* Enable the GMII GTX external clock
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* Use double data rate (DDR mode)
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*/
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vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
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CPU_PORT,
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VSC73XX_ADVPORTM,
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VSC73XX_ADVPORTM_EXT_PORT |
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VSC73XX_ADVPORTM_ENA_GTX |
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VSC73XX_ADVPORTM_DDR_MODE);
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}
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/* This is the MAC confiuration that always need to happen
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* after a PHY or the CPU port comes up or down.
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*/
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if (!phydev->link) {
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int ret, err;
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dev_dbg(vsc->dev, "port %d: went down\n",
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port);
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/* Disable RX on this port */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
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VSC73XX_MAC_CFG,
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VSC73XX_MAC_CFG_RX_EN, 0);
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/* Discard packets */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
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VSC73XX_ARBDISC, BIT(port), BIT(port));
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/* Wait until queue is empty */
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ret = read_poll_timeout(vsc73xx_read, err,
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err < 0 || (val & BIT(port)),
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VSC73XX_POLL_SLEEP_US,
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VSC73XX_POLL_TIMEOUT_US, false,
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vsc, VSC73XX_BLOCK_ARBITER, 0,
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VSC73XX_ARBEMPTY, &val);
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if (ret)
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dev_err(vsc->dev,
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"timeout waiting for block arbiter\n");
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else if (err < 0)
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dev_err(vsc->dev, "error reading arbiter\n");
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/* Put this port into reset */
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vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG,
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VSC73XX_MAC_CFG_RESET);
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/* Accept packets again */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
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VSC73XX_ARBDISC, BIT(port), 0);
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/* Allow backward dropping of frames from this port */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
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VSC73XX_SBACKWDROP, BIT(port), BIT(port));
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/* Receive mask (disable forwarding) */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
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VSC73XX_RECVMASK, BIT(port), 0);
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return;
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}
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/* Figure out what speed was negotiated */
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if (phydev->speed == SPEED_1000) {
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dev_dbg(vsc->dev, "port %d: 1000 Mbit mode full duplex\n",
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port);
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/* Set up default for internal port or external RGMII */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
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val = VSC73XX_MAC_CFG_1000M_F_RGMII;
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else
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val = VSC73XX_MAC_CFG_1000M_F_PHY;
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vsc73xx_adjust_enable_port(vsc, port, phydev, val);
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} else if (phydev->speed == SPEED_100) {
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if (phydev->duplex == DUPLEX_FULL) {
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val = VSC73XX_MAC_CFG_100_10M_F_PHY;
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dev_dbg(vsc->dev,
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"port %d: 100 Mbit full duplex mode\n",
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port);
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} else {
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val = VSC73XX_MAC_CFG_100_10M_H_PHY;
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dev_dbg(vsc->dev,
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"port %d: 100 Mbit half duplex mode\n",
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port);
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}
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vsc73xx_adjust_enable_port(vsc, port, phydev, val);
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} else if (phydev->speed == SPEED_10) {
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if (phydev->duplex == DUPLEX_FULL) {
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val = VSC73XX_MAC_CFG_100_10M_F_PHY;
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dev_dbg(vsc->dev,
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"port %d: 10 Mbit full duplex mode\n",
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port);
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} else {
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val = VSC73XX_MAC_CFG_100_10M_H_PHY;
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dev_dbg(vsc->dev,
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"port %d: 10 Mbit half duplex mode\n",
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port);
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}
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vsc73xx_adjust_enable_port(vsc, port, phydev, val);
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} else {
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dev_err(vsc->dev,
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"could not adjust link: unknown speed\n");
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}
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/* Enable port (forwarding) in the receieve mask */
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vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
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VSC73XX_RECVMASK, BIT(port), BIT(port));
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}
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static int vsc73xx_port_enable(struct dsa_switch *ds, int port,
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struct phy_device *phy)
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{
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@ -1055,12 +1039,17 @@ static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port,
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config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000;
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}
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static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = {
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.mac_config = vsc73xx_mac_config,
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.mac_link_down = vsc73xx_mac_link_down,
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.mac_link_up = vsc73xx_mac_link_up,
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};
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static const struct dsa_switch_ops vsc73xx_ds_ops = {
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.get_tag_protocol = vsc73xx_get_tag_protocol,
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.setup = vsc73xx_setup,
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.phy_read = vsc73xx_phy_read,
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.phy_write = vsc73xx_phy_write,
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.adjust_link = vsc73xx_adjust_link,
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.get_strings = vsc73xx_get_strings,
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.get_ethtool_stats = vsc73xx_get_ethtool_stats,
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.get_sset_count = vsc73xx_get_sset_count,
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@ -1217,6 +1206,7 @@ int vsc73xx_probe(struct vsc73xx *vsc)
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vsc->ds->priv = vsc;
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vsc->ds->ops = &vsc73xx_ds_ops;
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vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops;
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ret = dsa_register_switch(vsc->ds);
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if (ret) {
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dev_err(dev, "unable to register switch (%d)\n", ret);
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