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arm64: dts: mediatek: mt8395-genio-1200-evk: Add display on DSI0
This board has a Startek KD070FHFID078 MIPI-DSI panel on the DSI0 connector, so add and configure the pipeline connecting VDOSYS0 components to DSI0, with the needed pinctrl and display nodes in devicetree. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Link: https://lore.kernel.org/r/20250224-mt8395-genio-1200-evk-enable-dsi-panel-v1-1-74f31cf48a43@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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@ -91,13 +91,12 @@ apu_mem: memory@62000000 {
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};
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};
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backlight_lcd0: backlight-lcd0 {
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backlight_lcm0: backlight-lcm0 {
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compatible = "pwm-backlight";
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pwms = <&disp_pwm0 0 500000>;
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enable-gpios = <&pio 47 GPIO_ACTIVE_HIGH>;
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brightness-levels = <0 1023>;
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num-interpolated-steps = <1023>;
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default-brightness-level = <576>;
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num-interpolated-steps = <1023>;
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pwms = <&disp_pwm0 0 500000>;
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};
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backlight_lcd1: backlight-lcd1 {
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@ -150,6 +149,24 @@ button-volume-up {
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};
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};
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lcm0_iovcc: regulator-vio18-lcm0 {
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compatible = "regulator-fixed";
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regulator-name = "vio18_lcm0";
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enable-active-high;
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gpio = <&pio 47 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&dsi0_vreg_en_pins>;
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vin-supply = <&mt6360_ldo2>;
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};
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lcm0_vddp: regulator-vsys-lcm0 {
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compatible = "regulator-fixed";
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regulator-name = "vsys_lcm0";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&mt6360_ldo1>;
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};
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wifi_fixed_3v3: regulator-2 {
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compatible = "regulator-fixed";
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regulator-name = "wifi_3v3";
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@ -163,14 +180,65 @@ wifi_fixed_3v3: regulator-2 {
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&disp_pwm0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_default_pins>;
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pinctrl-0 = <&disp_pwm0_pins>;
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status = "okay";
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};
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&dither0_in {
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remote-endpoint = <&gamma0_out>;
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};
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&dither0_out {
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remote-endpoint = <&dsi0_in>;
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};
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&dmic_codec {
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wakeup-delay-ms = <200>;
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};
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&dsi0 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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panel@0 {
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compatible = "startek,kd070fhfid078", "himax,hx8279";
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reg = <0>;
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backlight = <&backlight_lcm0>;
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enable-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&pio 108 GPIO_ACTIVE_HIGH>;
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iovcc-supply = <&lcm0_iovcc>;
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vdd-supply = <&lcm0_vddp>;
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pinctrl-names = "default";
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pinctrl-0 = <&panel_default_pins>;
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port {
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dsi_panel_in: endpoint {
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remote-endpoint = <&dsi0_out>;
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dither0_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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remote-endpoint = <&dsi_panel_in>;
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};
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};
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};
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};
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ð {
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phy-mode ="rgmii-rxid";
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phy-handle = <ð_phy0>;
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@ -194,6 +262,10 @@ eth_phy0: ethernet-phy@1 {
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};
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};
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&gamma0_out {
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remote-endpoint = <&dither0_in>;
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};
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&gpu {
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mali-supply = <&mt6315_7_vbuck1>;
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status = "okay";
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@ -418,6 +490,10 @@ &mfg1 {
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domain-supply = <&mt6359_vsram_others_ldo_reg>;
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};
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&mipi_tx0 {
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status = "okay";
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};
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&mmc0 {
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status = "okay";
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pinctrl-names = "default", "state_uhs";
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@ -500,6 +576,10 @@ &mt6359codec {
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mediatek,mic-type-2 = <1>; /* ACC */
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};
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&ovl0_in {
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remote-endpoint = <&vdosys0_ep_main>;
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};
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&pcie0 {
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pinctrl-names = "default", "idle";
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pinctrl-0 = <&pcie0_default_pins>;
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@ -777,6 +857,25 @@ pins {
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};
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};
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dsi0_vreg_en_pins: dsi0-vreg-en-pins {
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pins-pwr-en {
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pinmux = <PINMUX_GPIO47__FUNC_GPIO47>;
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output-low;
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};
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};
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panel_default_pins: panel-default-pins {
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pins-rst {
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pinmux = <PINMUX_GPIO108__FUNC_GPIO108>;
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output-high;
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};
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pins-en {
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pinmux = <PINMUX_GPIO48__FUNC_GPIO48>;
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output-low;
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};
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};
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pcie0_default_pins: pcie0-default-pins {
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pins {
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pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
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@ -803,8 +902,8 @@ pins {
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};
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};
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pwm0_default_pins: pwm0-default-pins {
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pins-cmd-dat {
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disp_pwm0_pins: disp-pwm0-pins {
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pins-disp-pwm {
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pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>;
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};
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};
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@ -1015,6 +1114,18 @@ &ssusb3 {
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status = "okay";
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};
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&vdosys0 {
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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vdosys0_ep_main: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ovl0_in>;
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};
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};
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};
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&xhci0 {
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status = "okay";
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};
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