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arm64: dts: apm/shadowcat: More clock clean-ups

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A fixed-factor-clock only provides 1 clock, so "#clock-cells" must be 0.

The "snps,designware-i2c" node is not a clock provider, so drop
"#clock-cells.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251216-dt-apm-v1-1-0bf2bf8b982c@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Rob Herring (Arm) 2025-12-16 14:27:48 -06:00 committed by Krzysztof Kozlowski
parent 7dd84bbec2
commit 21bd5fb461
1 changed files with 8 additions and 9 deletions
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17
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
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@ -295,7 +295,7 @@ socpll: socpll@17000120 {
socplldiv2: socplldiv2 {
compatible = "fixed-factor-clock";
#clock-cells = <1>;
#clock-cells = <0>;
clocks = <&socpll 0>;
clock-mult = <1>;
clock-div = <2>;
@ -305,7 +305,7 @@ socplldiv2: socplldiv2 {
ahbclk: ahbclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clocks = <&socplldiv2>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "div-reg";
divider-offset = <0x164>;
@ -329,7 +329,7 @@ sbapbclk: sbapbclk@1704c000 {
sdioclk: sdioclk@1f2ac000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clocks = <&socplldiv2>;
reg = <0x0 0x1f2ac000 0x0 0x1000
0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg", "div-reg";
@ -346,7 +346,7 @@ sdioclk: sdioclk@1f2ac000 {
pcie0clk: pcie0clk@1f2bc000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clocks = <&socplldiv2>;
reg = <0x0 0x1f2bc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie0clk";
@ -355,7 +355,7 @@ pcie0clk: pcie0clk@1f2bc000 {
pcie1clk: pcie1clk@1f2cc000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clocks = <&socplldiv2>;
reg = <0x0 0x1f2cc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie1clk";
@ -364,7 +364,7 @@ pcie1clk: pcie1clk@1f2cc000 {
xge0clk: xge0clk@1f61c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clocks = <&socplldiv2>;
reg = <0x0 0x1f61c000 0x0 0x1000>;
reg-names = "csr-reg";
enable-mask = <0x3>;
@ -375,7 +375,7 @@ xge0clk: xge0clk@1f61c000 {
xge1clk: xge1clk@1f62c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clocks = <&socplldiv2>;
reg = <0x0 0x1f62c000 0x0 0x1000>;
reg-names = "csr-reg";
enable-mask = <0x3>;
@ -386,7 +386,7 @@ xge1clk: xge1clk@1f62c000 {
rngpkaclk: rngpkaclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clocks = <&socplldiv2>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg";
csr-offset = <0xc>;
@ -799,7 +799,6 @@ i2c1: i2c@10511000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x10511000 0x0 0x1000>;
interrupts = <0 0x45 0x4>;
#clock-cells = <1>;
clocks = <&sbapbclk 0>;
};