From 21ac5604d31d5927cb6369d2be8a22734610918e Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Wed, 7 Feb 2018 09:55:20 +0800 Subject: [PATCH] soc: rockchip: fiq debugger: clear busy interrupt before ATF fiq init If uart has busy interrupt before ATF fiq init, although IER is 0, it would cause interrupt. Thus after enable uart fiq of gic during init, it may cause infinite interrupt because there is no uart handler to clear the interrupts. Change-Id: If530d266068e25132206519e5bf41762f6a7c9bd Signed-off-by: Huibin Hong --- drivers/soc/rockchip/rk_fiq_debugger.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/rockchip/rk_fiq_debugger.c b/drivers/soc/rockchip/rk_fiq_debugger.c index 964d26f0dea1..1986e6373c50 100755 --- a/drivers/soc/rockchip/rk_fiq_debugger.c +++ b/drivers/soc/rockchip/rk_fiq_debugger.c @@ -466,6 +466,8 @@ void rk_serial_debug_init(void __iomem *base, phys_addr_t phy_base, goto out3; } + /* clear busy interrupt, make sure all interrupts are disabled */ + rk_fiq_read(t, UART_USR); #ifdef CONFIG_FIQ_DEBUGGER_TRUST_ZONE if ((signal_irq > 0) && (serial_hwirq > 0)) { ret = fiq_debugger_bind_sip_smc(t, phy_base, serial_hwirq,