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Allwinner clk changes for 6.14

Browse Source 
Instead of forcing a particular clock parent for TCON0 on the A64,
 the decision is left to the device tree. Which clock parent gets
 assigned depends on which display output is used. If the wrong
 parent is assigned, the display doesn't work.
 
 Patches include adding the clock parents to the DT binding (which
 is shared with the DT tree), removing the now redundant macros from
 the clock driver, and stop forcing a particular clock parent in the
 driver.
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Merge tag 'sunxi-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Chen-Yu Tsai:

Instead of forcing a particular clock parent for TCON0 on the A64,
the decision is left to the device tree. Which clock parent gets
assigned depends on which display output is used. If the wrong
parent is assigned, the display doesn't work.

Patches include adding the clock parents to the DT binding (which
is shared with the DT tree), removing the now redundant macros from
the clock driver, and stop forcing a particular clock parent in the
driver.

* tag 'sunxi-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent
  clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI
  dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
This commit is contained in:
Stephen Boyd 2025-01-08 11:57:24 -08:00
commit 214e7a51f7
3 changed files with 6 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
View File

@ -535,11 +535,11 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
CLK_SET_RATE_PARENT);
/*
* DSI output seems to work only when PLL_MIPI selected. Set it and prevent
* the mux from reparenting.
* Experiments showed that RGB output requires pll-video0-2x, while DSI
* requires pll-mipi. It will not work with incorrect clock, the screen will
* be blank.
* sun50i-a64.dtsi assigns pll-mipi as TCON0 parent by default
*/
#define SUN50I_A64_TCON0_CLK_REG 0x118
static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
static const u8 tcon0_table[] = { 0, 2, };
static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents,
@ -959,11 +959,6 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
/* Set PLL MIPI as parent for TCON0 */
val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
val &= ~GENMASK(26, 24);
writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
if (ret)
return ret;

2
drivers/clk/sunxi-ng/ccu-sun50i-a64.h
View File

@ -21,7 +21,6 @@
/* PLL_VIDEO0 exported for HDMI PHY */
#define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_VE 9
#define CLK_PLL_DDR0 10
@ -32,7 +31,6 @@
#define CLK_PLL_PERIPH1_2X 14
#define CLK_PLL_VIDEO1 15
#define CLK_PLL_GPU 16
#define CLK_PLL_MIPI 17
#define CLK_PLL_HSIC 18
#define CLK_PLL_DE 19
#define CLK_PLL_DDR1 20

2
include/dt-bindings/clock/sun50i-a64-ccu.h
View File

@ -44,7 +44,9 @@
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
#define CLK_PLL_VIDEO0 7
#define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_PERIPH0 11
#define CLK_PLL_MIPI 17
#define CLK_CPUX 21
#define CLK_BUS_MIPI_DSI 28