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drm/amd/display: Update static soc table
[WHY] Update the static soc table dcn3_5_soc. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -159,7 +159,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
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.dppclk_mhz = 1200.0,
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.phyclk_mhz = 810.0,
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.phyclk_d18_mhz = 667.0,
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.dscclk_mhz = 417.0,
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.dscclk_mhz = 400.0,
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.dtbclk_mhz = 600.0,
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},
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},
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