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https://github.com/torvalds/linux.git
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Merge branch 'pci/virtualization'
- Mark ASM1164 SATA controller to avoid bus reset since it fails to train the Link after reset (Alex Williamson) - Mark Nvidia GB10 Root Ports to avoid bus reset since they may fail to retrain the link after reset (Johnny-CC Chang) - Add lockdep and other lock assertions (Ilpo Järvinen) - Add ACS quirk for Qualcomm Hamoa & Glymur, which provides ACS-like features but doesn't advertise an ACS Capability (Krishna Chaitanya Chundru) - Add ACS quirk for Pericom PI7C9X2G404 switches, which fail under load when P2P Redirect Request is enabled (Nicolas Cavallari) - Remove an incorrect unlock in pci_slot_trylock() error handling (Jinhui Guo) - Lock the bridge device for slot reset (Keith Busch) - Enable ACS after IOMMU configuration on OF platforms so ACS is enabled an all devices; previously the first device enumeration (typically a Root Port) was omitted (Manivannan Sadhasivam) - Disable ACS Source Validation for IDT 0x80b5 and 0x8090 switches to work around hardware erratum; previously ACS SV was temporarily disabled, which worked for enumeration but not after reset (Manivannan Sadhasivam) * pci/virtualization: PCI: Disable ACS SV for IDT 0x8090 switch PCI: Disable ACS SV for IDT 0x80b5 switch PCI: Cache ACS Capabilities register PCI: Enable ACS after configuring IOMMU for OF platforms PCI: Add ACS quirk for Pericom PI7C9X2G404 switches [12d8:b404] PCI: Add ACS quirk for Qualcomm Hamoa & Glymur PCI: Use device_lock_assert() to verify device lock is held PCI: Use lockdep_assert_held(pci_bus_sem) to verify lock is held PCI: Fix pci_slot_lock () device locking PCI: Fix pci_slot_trylock() error handling PCI: Mark Nvidia GB10 to avoid bus reset PCI: Mark ASM1164 SATA controller to avoid bus reset
This commit is contained in:
Bjorn Helgaas
commit
2095b9dd2e
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@ -1650,6 +1650,14 @@ static int pci_dma_configure(struct device *dev)
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ret = acpi_dma_configure(dev, acpi_get_dma_attr(adev));
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}
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/*
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* Attempt to enable ACS regardless of capability because some Root
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* Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
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* the standard ACS capability but still support ACS via those
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* quirks.
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*/
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pci_enable_acs(to_pci_dev(dev));
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pci_put_host_bridge_device(bridge);
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/* @drv may not be valid when we're called from the IOMMU layer */
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@ -13,6 +13,7 @@
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#include <linux/delay.h>
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#include <linux/dmi.h>
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#include <linux/init.h>
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#include <linux/lockdep.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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@ -886,7 +887,6 @@ static const char *disable_acs_redir_param;
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static const char *config_acs_param;
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struct pci_acs {
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u16 cap;
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u16 ctrl;
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u16 fw_ctrl;
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};
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@ -989,27 +989,27 @@ static void __pci_config_acs(struct pci_dev *dev, struct pci_acs *caps,
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static void pci_std_enable_acs(struct pci_dev *dev, struct pci_acs *caps)
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{
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/* Source Validation */
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caps->ctrl |= (caps->cap & PCI_ACS_SV);
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caps->ctrl |= (dev->acs_capabilities & PCI_ACS_SV);
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/* P2P Request Redirect */
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caps->ctrl |= (caps->cap & PCI_ACS_RR);
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caps->ctrl |= (dev->acs_capabilities & PCI_ACS_RR);
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/* P2P Completion Redirect */
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caps->ctrl |= (caps->cap & PCI_ACS_CR);
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caps->ctrl |= (dev->acs_capabilities & PCI_ACS_CR);
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/* Upstream Forwarding */
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caps->ctrl |= (caps->cap & PCI_ACS_UF);
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caps->ctrl |= (dev->acs_capabilities & PCI_ACS_UF);
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/* Enable Translation Blocking for external devices and noats */
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if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
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caps->ctrl |= (caps->cap & PCI_ACS_TB);
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caps->ctrl |= (dev->acs_capabilities & PCI_ACS_TB);
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}
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/**
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* pci_enable_acs - enable ACS if hardware support it
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* @dev: the PCI device
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*/
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static void pci_enable_acs(struct pci_dev *dev)
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void pci_enable_acs(struct pci_dev *dev)
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{
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struct pci_acs caps;
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bool enable_acs = false;
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@ -1025,7 +1025,6 @@ static void pci_enable_acs(struct pci_dev *dev)
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if (!pos)
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return;
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pci_read_config_word(dev, pos + PCI_ACS_CAP, &caps.cap);
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pci_read_config_word(dev, pos + PCI_ACS_CTRL, &caps.ctrl);
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caps.fw_ctrl = caps.ctrl;
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@ -3517,7 +3516,7 @@ void pci_configure_ari(struct pci_dev *dev)
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static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
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{
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int pos;
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u16 cap, ctrl;
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u16 ctrl;
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pos = pdev->acs_cap;
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if (!pos)
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@ -3528,8 +3527,7 @@ static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
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* or only required if controllable. Features missing from the
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* capability field can therefore be assumed as hard-wired enabled.
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*/
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pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
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acs_flags &= (cap | PCI_ACS_EC);
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acs_flags &= (pdev->acs_capabilities | PCI_ACS_EC);
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pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
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return (ctrl & acs_flags) == acs_flags;
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@ -3650,15 +3648,15 @@ bool pci_acs_path_enabled(struct pci_dev *start,
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*/
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void pci_acs_init(struct pci_dev *dev)
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{
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dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
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int pos;
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/*
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* Attempt to enable ACS regardless of capability because some Root
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* Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
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* the standard ACS capability but still support ACS via those
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* quirks.
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*/
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pci_enable_acs(dev);
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dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
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pos = dev->acs_cap;
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if (!pos)
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return;
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pci_read_config_word(dev, pos + PCI_ACS_CAP, &dev->acs_capabilities);
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pci_disable_broken_acs_cap(dev);
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}
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/**
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@ -4625,7 +4623,7 @@ bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
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* spec says 100 ms, but firmware can lower it and we allow drivers to
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* increase it as well.
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*
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* Called with @pci_bus_sem locked for reading.
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* Context: Called with @pci_bus_sem locked for reading.
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*/
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static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
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{
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@ -4633,6 +4631,8 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
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int min_delay = 100;
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int max_delay = 0;
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lockdep_assert_held(&pci_bus_sem);
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list_for_each_entry(pdev, &bus->devices, bus_list) {
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if (pdev->d3cold_delay < min_delay)
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min_delay = pdev->d3cold_delay;
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@ -4970,6 +4970,7 @@ static void pci_dev_save_and_disable(struct pci_dev *dev)
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* races with ->remove() by the device lock, which must be held by
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* the caller.
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*/
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device_lock_assert(&dev->dev);
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if (err_handler && err_handler->reset_prepare)
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err_handler->reset_prepare(dev);
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else if (dev->driver)
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@ -5040,7 +5041,9 @@ const struct pci_reset_fn_method pci_reset_fn_methods[] = {
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* device including MSI, bus mastering, BARs, decoding IO and memory spaces,
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* etc.
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*
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* Returns 0 if the device function was successfully reset or negative if the
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* Context: The caller must hold the device lock.
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*
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* Return: 0 if the device function was successfully reset or negative if the
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* device doesn't support resetting a single function.
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*/
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int __pci_reset_function_locked(struct pci_dev *dev)
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@ -5049,6 +5052,7 @@ int __pci_reset_function_locked(struct pci_dev *dev)
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const struct pci_reset_fn_method *method;
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might_sleep();
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device_lock_assert(&dev->dev);
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/*
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* A reset method returns -ENOTTY if it doesn't support this device and
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@ -5171,13 +5175,17 @@ EXPORT_SYMBOL_GPL(pci_reset_function);
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* over the reset. It also differs from pci_reset_function() in that it
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* requires the PCI device lock to be held.
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*
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* Returns 0 if the device function was successfully reset or negative if the
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* Context: The caller must hold the device lock.
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*
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* Return: 0 if the device function was successfully reset or negative if the
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* device doesn't support resetting a single function.
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*/
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int pci_reset_function_locked(struct pci_dev *dev)
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{
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int rc;
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device_lock_assert(&dev->dev);
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if (!pci_reset_supported(dev))
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return -ENOTTY;
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@ -5293,10 +5301,9 @@ static int pci_bus_trylock(struct pci_bus *bus)
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/* Do any devices on or below this slot prevent a bus reset? */
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static bool pci_slot_resettable(struct pci_slot *slot)
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{
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struct pci_dev *dev;
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struct pci_dev *dev, *bridge = slot->bus->self;
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if (slot->bus->self &&
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(slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
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if (bridge && (bridge->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
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return false;
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list_for_each_entry(dev, &slot->bus->devices, bus_list) {
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@ -5313,7 +5320,10 @@ static bool pci_slot_resettable(struct pci_slot *slot)
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/* Lock devices from the top of the tree down */
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static void pci_slot_lock(struct pci_slot *slot)
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{
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struct pci_dev *dev;
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struct pci_dev *dev, *bridge = slot->bus->self;
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if (bridge)
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pci_dev_lock(bridge);
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list_for_each_entry(dev, &slot->bus->devices, bus_list) {
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if (!dev->slot || dev->slot != slot)
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@ -5328,7 +5338,7 @@ static void pci_slot_lock(struct pci_slot *slot)
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/* Unlock devices from the bottom of the tree up */
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static void pci_slot_unlock(struct pci_slot *slot)
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{
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struct pci_dev *dev;
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struct pci_dev *dev, *bridge = slot->bus->self;
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list_for_each_entry(dev, &slot->bus->devices, bus_list) {
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if (!dev->slot || dev->slot != slot)
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@ -5338,21 +5348,25 @@ static void pci_slot_unlock(struct pci_slot *slot)
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else
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pci_dev_unlock(dev);
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}
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if (bridge)
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pci_dev_unlock(bridge);
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}
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/* Return 1 on successful lock, 0 on contention */
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static int pci_slot_trylock(struct pci_slot *slot)
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{
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struct pci_dev *dev;
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struct pci_dev *dev, *bridge = slot->bus->self;
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if (bridge && !pci_dev_trylock(bridge))
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return 0;
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list_for_each_entry(dev, &slot->bus->devices, bus_list) {
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if (!dev->slot || dev->slot != slot)
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continue;
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if (dev->subordinate) {
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if (!pci_bus_trylock(dev->subordinate)) {
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pci_dev_unlock(dev);
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if (!pci_bus_trylock(dev->subordinate))
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goto unlock;
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}
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} else if (!pci_dev_trylock(dev))
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goto unlock;
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}
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@ -5368,6 +5382,9 @@ static int pci_slot_trylock(struct pci_slot *slot)
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else
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pci_dev_unlock(dev);
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}
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if (bridge)
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pci_dev_unlock(bridge);
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return 0;
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}
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|
|
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|
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@ -469,7 +469,6 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int rrs_timeout);
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bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int rrs_timeout);
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int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout);
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int pci_setup_device(struct pci_dev *dev);
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void __pci_size_stdbars(struct pci_dev *dev, int count,
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@ -1000,10 +999,12 @@ static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
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}
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void pci_acs_init(struct pci_dev *dev);
|
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void pci_enable_acs(struct pci_dev *dev);
|
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#ifdef CONFIG_PCI_QUIRKS
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int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
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int pci_dev_specific_enable_acs(struct pci_dev *dev);
|
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int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
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void pci_disable_broken_acs_cap(struct pci_dev *pdev);
|
||||
int pcie_failed_link_retrain(struct pci_dev *dev);
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#else
|
||||
static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
|
||||
|
|
@ -1019,6 +1020,7 @@ static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
|
|||
{
|
||||
return -ENOTTY;
|
||||
}
|
||||
static inline void pci_disable_broken_acs_cap(struct pci_dev *dev) { }
|
||||
static inline int pcie_failed_link_retrain(struct pci_dev *dev)
|
||||
{
|
||||
return -ENOTTY;
|
||||
|
|
|
|||
|
|
@ -2549,18 +2549,6 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
|
|||
bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
|
||||
int timeout)
|
||||
{
|
||||
#ifdef CONFIG_PCI_QUIRKS
|
||||
struct pci_dev *bridge = bus->self;
|
||||
|
||||
/*
|
||||
* Certain IDT switches have an issue where they improperly trigger
|
||||
* ACS Source Validation errors on completions for config reads.
|
||||
*/
|
||||
if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
|
||||
bridge->device == 0x80b5)
|
||||
return pci_idt_bus_quirk(bus, devfn, l, timeout);
|
||||
#endif
|
||||
|
||||
return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
|
||||
|
|
|
|||
|
|
@ -3758,6 +3758,14 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
|
|||
dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
|
||||
}
|
||||
|
||||
/*
|
||||
* After asserting Secondary Bus Reset to downstream devices via a GB10
|
||||
* Root Port, the link may not retrain correctly.
|
||||
* https://lore.kernel.org/r/20251113084441.2124737-1-Johnny-CC.Chang@mediatek.com
|
||||
*/
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22CE, quirk_no_bus_reset);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22D0, quirk_no_bus_reset);
|
||||
|
||||
/*
|
||||
* Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
|
||||
* prevented for those affected devices.
|
||||
|
|
@ -3801,6 +3809,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
|
|||
*/
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
|
||||
|
||||
/*
|
||||
* Reports from users making use of PCI device assignment with ASM1164
|
||||
* controllers indicate an issue with bus reset where the device fails to
|
||||
* retrain. The issue appears more common in configurations with multiple
|
||||
* controllers. The device does indicate PM reset support (NoSoftRst-),
|
||||
* therefore this still leaves a viable reset method.
|
||||
* https://forum.proxmox.com/threads/problems-with-pcie-passthrough-with-two-identical-devices.149003/
|
||||
*/
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1164, quirk_no_bus_reset);
|
||||
|
||||
static void quirk_no_pm_reset(struct pci_dev *dev)
|
||||
{
|
||||
/*
|
||||
|
|
@ -5127,6 +5145,10 @@ static const struct pci_dev_acs_enabled {
|
|||
{ PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
|
||||
/* QCOM SA8775P root port */
|
||||
{ PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs },
|
||||
/* QCOM Hamoa root port */
|
||||
{ PCI_VENDOR_ID_QCOM, 0x0111, pci_quirk_qcom_rp_acs },
|
||||
/* QCOM Glymur root port */
|
||||
{ PCI_VENDOR_ID_QCOM, 0x0120, pci_quirk_qcom_rp_acs },
|
||||
/* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
|
||||
{ PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
|
||||
/* Intel PCH root ports */
|
||||
|
|
@ -5800,7 +5822,7 @@ DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
|
|||
|
||||
/*
|
||||
* Some IDT switches incorrectly flag an ACS Source Validation error on
|
||||
* completions for config read requests even though PCIe r4.0, sec
|
||||
* completions for config read requests even though PCIe r7.0, sec
|
||||
* 6.12.1.1, says that completions are never affected by ACS Source
|
||||
* Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
|
||||
*
|
||||
|
|
@ -5813,44 +5835,20 @@ DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
|
|||
*
|
||||
* The workaround suggested by IDT is to issue a config write to the
|
||||
* downstream device before issuing the first config read. This allows the
|
||||
* downstream device to capture its bus and device numbers (see PCIe r4.0,
|
||||
* sec 2.2.9), thus avoiding the ACS error on the completion.
|
||||
* downstream device to capture its bus and device numbers (see PCIe r7.0,
|
||||
* sec 2.2.9.1), thus avoiding the ACS error on the completion.
|
||||
*
|
||||
* However, we don't know when the device is ready to accept the config
|
||||
* write, so we do config reads until we receive a non-Config Request Retry
|
||||
* Status, then do the config write.
|
||||
*
|
||||
* To avoid hitting the erratum when doing the config reads, we disable ACS
|
||||
* SV around this process.
|
||||
* write, and the issue affects resets of the switch as well as enumeration,
|
||||
* so disable use of ACS SV for these devices altogether.
|
||||
*/
|
||||
int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
|
||||
void pci_disable_broken_acs_cap(struct pci_dev *pdev)
|
||||
{
|
||||
int pos;
|
||||
u16 ctrl = 0;
|
||||
bool found;
|
||||
struct pci_dev *bridge = bus->self;
|
||||
|
||||
pos = bridge->acs_cap;
|
||||
|
||||
/* Disable ACS SV before initial config reads */
|
||||
if (pos) {
|
||||
pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
|
||||
if (ctrl & PCI_ACS_SV)
|
||||
pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
|
||||
ctrl & ~PCI_ACS_SV);
|
||||
if (pdev->vendor == PCI_VENDOR_ID_IDT &&
|
||||
(pdev->device == 0x80b5 || pdev->device == 0x8090)) {
|
||||
pci_info(pdev, "Disabling broken ACS SV; downstream device isolation reduced\n");
|
||||
pdev->acs_capabilities &= ~PCI_ACS_SV;
|
||||
}
|
||||
|
||||
found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
|
||||
|
||||
/* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
|
||||
if (found)
|
||||
pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
|
||||
|
||||
/* Re-enable ACS_SV if it was previously enabled */
|
||||
if (ctrl & PCI_ACS_SV)
|
||||
pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
|
||||
|
||||
return found;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -6209,6 +6207,10 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
|
|||
pci_fixup_pericom_acs_store_forward);
|
||||
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
|
||||
pci_fixup_pericom_acs_store_forward);
|
||||
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0xb404,
|
||||
pci_fixup_pericom_acs_store_forward);
|
||||
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0xb404,
|
||||
pci_fixup_pericom_acs_store_forward);
|
||||
|
||||
static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -564,6 +564,7 @@ struct pci_dev {
|
|||
struct pci_tsm *tsm; /* TSM operation state */
|
||||
#endif
|
||||
u16 acs_cap; /* ACS Capability offset */
|
||||
u16 acs_capabilities; /* ACS Capabilities */
|
||||
u8 supported_speeds; /* Supported Link Speeds Vector */
|
||||
phys_addr_t rom; /* Physical address if not from BAR */
|
||||
size_t romlen; /* Length if not from BAR */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user