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drm/amd/amdgpu: Add soc_v1_0 reset handler
Add soc_v1_0 reset handler for mode2 reset v2: Remove XGMI parallel reset dispatch and xgmi_update_topology() call, reset on soc_v1_0 is per-device only. (Lijo) v3: Remove ras as will be plugged later as separate ip. Remove vcn from ip mask as vcn not part of reset sequence yet (Lijo) Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Asad Kamal
Alex Deucher
parent
93eca5a03b
commit
208e5d4b3f
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@ -30,6 +30,7 @@
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#include "sdma_v7_1.h"
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#include "gfx_v12_1.h"
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#include "amdgpu_video_codecs.h"
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#include "amdgpu_reset.h"
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#include "gc/gc_12_1_0_offset.h"
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#include "gc/gc_12_1_0_sh_mask.h"
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@ -398,6 +399,288 @@ const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = {
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.funcs = &soc_v1_0_common_ip_funcs,
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};
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static struct amdgpu_reset_handler *
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soc_v1_0_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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struct amdgpu_reset_handler *handler;
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enum amd_reset_method method;
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int i;
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method = (reset_context->method == AMD_RESET_METHOD_NONE) ?
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amdgpu_asic_reset_method(adev) : reset_context->method;
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for_each_handler(i, handler, reset_ctl) {
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if (handler->reset_method == method)
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return handler;
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}
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return NULL;
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}
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static inline u32 soc_v1_0_get_ip_block_mask(struct amdgpu_device *adev)
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{
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u32 ip_block_mask = BIT(AMD_IP_BLOCK_TYPE_GFX) |
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BIT(AMD_IP_BLOCK_TYPE_MES) |
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BIT(AMD_IP_BLOCK_TYPE_SDMA) |
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BIT(AMD_IP_BLOCK_TYPE_IH);
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return ip_block_mask;
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}
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static int soc_v1_0_mode2_suspend_ip(struct amdgpu_device *adev)
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{
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u32 ip_block_mask = soc_v1_0_get_ip_block_mask(adev);
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u32 ip_block;
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int r, i;
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amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
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/* SDMA suspend not required */
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ip_block_mask &= ~BIT(AMD_IP_BLOCK_TYPE_SDMA);
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for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
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if (!adev->ip_blocks[i].status.valid)
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continue;
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ip_block = BIT(adev->ip_blocks[i].version->type);
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if (!(ip_block_mask & ip_block))
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continue;
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r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
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if (r)
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return r;
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}
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return 0;
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}
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static int
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soc_v1_0_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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return soc_v1_0_mode2_suspend_ip(adev);
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}
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static int soc_v1_0_mode2_reset(struct amdgpu_device *adev)
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{
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adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev);
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return adev->asic_reset_res;
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}
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static void soc_v1_0_async_reset(struct work_struct *work)
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{
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struct amdgpu_reset_handler *handler;
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struct amdgpu_reset_control *reset_ctl =
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container_of(work, struct amdgpu_reset_control, reset_work);
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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int i;
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for_each_handler(i, handler, reset_ctl) {
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if (handler->reset_method == reset_ctl->active_reset) {
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dev_dbg(adev->dev, "Resetting device\n");
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handler->do_reset(adev);
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break;
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}
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}
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}
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static int
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soc_v1_0_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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struct list_head *reset_device_list = reset_context->reset_device_list;
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struct amdgpu_device *tmp_adev = NULL;
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int r = 0;
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dev_dbg(adev->dev, "soc_v1_0 perform hw reset\n");
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if (!reset_device_list)
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return -EINVAL;
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list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
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mutex_lock(&tmp_adev->reset_cntl->reset_lock);
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tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;
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}
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list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
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r = soc_v1_0_mode2_reset(tmp_adev);
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if (r) {
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dev_err(tmp_adev->dev,
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"ASIC reset failed with error, %d for drm dev, %s",
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r, adev_to_drm(tmp_adev)->unique);
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break;
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}
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}
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list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
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mutex_unlock(&tmp_adev->reset_cntl->reset_lock);
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tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;
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}
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return r;
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}
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static int soc_v1_0_mode2_restore_ip(struct amdgpu_device *adev)
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{
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u32 ip_block_mask = soc_v1_0_get_ip_block_mask(adev);
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struct amdgpu_ip_block *ih_block;
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u32 ip_block;
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int i, r;
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if (ip_block_mask & BIT(AMD_IP_BLOCK_TYPE_IH)) {
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ih_block = amdgpu_device_ip_get_ip_block(adev,
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AMD_IP_BLOCK_TYPE_IH);
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if (unlikely(!ih_block)) {
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dev_err(adev->dev, "Failed to get IH handle\n");
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return -EINVAL;
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}
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r = amdgpu_ip_block_resume(ih_block);
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if (r)
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return r;
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}
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/* IH Block resume completed can be removed from ip_block_mask */
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ip_block_mask &= ~BIT(AMD_IP_BLOCK_TYPE_IH);
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/* Reinit GFXHUB */
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adev->gfxhub.funcs->init(adev);
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r = adev->gfxhub.funcs->gart_enable(adev);
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if (r) {
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dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
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return r;
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}
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (!adev->ip_blocks[i].status.valid)
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continue;
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ip_block = BIT(adev->ip_blocks[i].version->type);
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if (!(ip_block_mask & ip_block))
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continue;
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r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
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if (r)
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return r;
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}
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (!adev->ip_blocks[i].status.valid)
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continue;
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ip_block = BIT(adev->ip_blocks[i].version->type);
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if (!(ip_block_mask & ip_block))
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continue;
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if (adev->ip_blocks[i].version->funcs->late_init) {
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r = adev->ip_blocks[i].version->funcs->late_init(&adev->ip_blocks[i]);
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if (r) {
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dev_err(adev->dev,
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"late_init of IP block <%s> failed %d after reset\n",
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adev->ip_blocks[i].version->funcs->name,
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r);
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return r;
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}
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}
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adev->ip_blocks[i].status.late_initialized = true;
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}
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amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
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return r;
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}
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static int
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soc_v1_0_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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struct list_head *reset_device_list = reset_context->reset_device_list;
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struct amdgpu_device *tmp_adev = NULL;
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int r;
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if (!reset_device_list)
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return -EINVAL;
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list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
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amdgpu_set_init_level(tmp_adev,
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AMDGPU_INIT_LEVEL_RESET_RECOVERY);
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dev_info(tmp_adev->dev,
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"GPU reset succeeded, trying to resume\n");
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amdgpu_ras_clear_err_state(tmp_adev);
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r = soc_v1_0_mode2_restore_ip(tmp_adev);
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if (r)
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goto end;
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/*
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* Add this ASIC as tracked as reset was already
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* complete successfully.
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*/
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amdgpu_register_gpu_instance(tmp_adev);
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amdgpu_ras_resume(tmp_adev);
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if (!r) {
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amdgpu_set_init_level(tmp_adev,
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AMDGPU_INIT_LEVEL_DEFAULT);
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amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
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r = amdgpu_ib_ring_tests(tmp_adev);
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if (r) {
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dev_err(tmp_adev->dev,
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"ib ring test failed (%d).\n", r);
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r = -EAGAIN;
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tmp_adev->asic_reset_res = r;
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goto end;
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}
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}
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}
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end:
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return r;
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}
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static struct amdgpu_reset_handler soc_v1_0_mode2_handler = {
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.reset_method = AMD_RESET_METHOD_MODE2,
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.prepare_env = NULL,
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.prepare_hwcontext = soc_v1_0_mode2_prepare_hwcontext,
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.perform_reset = soc_v1_0_mode2_perform_reset,
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.restore_hwcontext = soc_v1_0_mode2_restore_hwcontext,
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.restore_env = NULL,
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.do_reset = soc_v1_0_mode2_reset,
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};
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static struct amdgpu_reset_handler
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*soc_v1_0_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = {
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&soc_v1_0_mode2_handler,
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};
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int soc_v1_0_reset_init(struct amdgpu_device *adev)
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{
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struct amdgpu_reset_control *reset_ctl;
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reset_ctl = kzalloc_obj(*reset_ctl, GFP_KERNEL);
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if (!reset_ctl)
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return -ENOMEM;
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reset_ctl->handle = adev;
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reset_ctl->async_reset = soc_v1_0_async_reset;
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reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
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reset_ctl->get_reset_handler = soc_v1_0_get_reset_handler;
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INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
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/* Only mode2 is handled through reset control now */
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reset_ctl->reset_handlers = &soc_v1_0_rst_handlers;
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adev->reset_cntl = reset_ctl;
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return 0;
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}
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int soc_v1_0_reset_fini(struct amdgpu_device *adev)
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{
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kfree(adev->reset_cntl);
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adev->reset_cntl = NULL;
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return 0;
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}
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static enum amdgpu_gfx_partition __soc_v1_0_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr)
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{
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struct amdgpu_device *adev = xcp_mgr->adev;
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@ -36,5 +36,7 @@ bool soc_v1_0_mid1_reg_range(uint32_t reg);
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uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg);
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uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg);
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u64 soc_v1_0_encode_ext_smn_addressing(int ext_id);
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int soc_v1_0_reset_init(struct amdgpu_device *adev);
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int soc_v1_0_reset_fini(struct amdgpu_device *adev);
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#endif
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