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dt-bindings: dma: Convert fsl,elo*-dma to YAML
The devicetree bindings for Freescale DMA engines have so far existed as a text file. This patch converts them to YAML, and specifies all the compatible strings currently in use in arch/powerpc/boot/dts. Signed-off-by: J. Neuschäfer <j.ne@posteo.net> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250308-ppcyaml-dma-v4-1-20392ea81ec6@posteo.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
J. Neuschäfer
Vinod Koul
parent
964c032d1d
commit
1fe283e850
137
Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
Normal file
137
Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml
Normal file
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@ -0,0 +1,137 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Elo DMA Controller
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maintainers:
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- J. Neuschäfer <j.ne@posteo.net>
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description:
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This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
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series chips such as mpc8315, mpc8349, mpc8379 etc.
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properties:
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compatible:
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items:
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- enum:
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- fsl,mpc8313-dma
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- fsl,mpc8315-dma
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- fsl,mpc8323-dma
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- fsl,mpc8347-dma
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- fsl,mpc8349-dma
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- fsl,mpc8360-dma
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- fsl,mpc8377-dma
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- fsl,mpc8378-dma
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- fsl,mpc8379-dma
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- const: fsl,elo-dma
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reg:
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items:
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- description:
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DMA General Status Register, i.e. DGSR which contains status for
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all the 4 DMA channels.
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Controller index. 0 for controller @ 0x8100.
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ranges: true
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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interrupts:
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maxItems: 1
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description: Controller interrupt.
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required:
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- compatible
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- reg
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patternProperties:
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"^dma-channel@[0-9a-f]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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oneOf:
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# native DMA channel
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- items:
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- enum:
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- fsl,mpc8315-dma-channel
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- fsl,mpc8323-dma-channel
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- fsl,mpc8347-dma-channel
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- fsl,mpc8349-dma-channel
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- fsl,mpc8360-dma-channel
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- fsl,mpc8377-dma-channel
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- fsl,mpc8378-dma-channel
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- fsl,mpc8379-dma-channel
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- const: fsl,elo-dma-channel
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# audio DMA channel, see fsl,ssi.yaml
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- const: fsl,ssi-dma-channel
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reg:
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maxItems: 1
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cell-index:
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description: DMA channel index starts at 0.
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interrupts:
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maxItems: 1
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description:
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Per-channel interrupt. Only necessary if no controller interrupt has
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been provided.
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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dma@82a8 {
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compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x8100 0x1a4>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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...
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125
Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
Normal file
125
Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml
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@ -0,0 +1,125 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Elo3 DMA Controller
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maintainers:
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- J. Neuschäfer <j.ne@posteo.net>
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description:
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DMA controller which has same function as EloPlus except that Elo3 has 8
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channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
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series chips, such as t1040, t4240, b4860.
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properties:
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compatible:
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const: fsl,elo3-dma
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reg:
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items:
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- description:
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DMA General Status Registers starting from DGSR0, for channel 1~4
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- description:
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DMA General Status Registers starting from DGSR1, for channel 5~8
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ranges: true
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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interrupts:
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maxItems: 1
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patternProperties:
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"^dma-channel@[0-9a-f]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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enum:
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# native DMA channel
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- fsl,eloplus-dma-channel
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# audio DMA channel, see fsl,ssi.yaml
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- fsl,ssi-dma-channel
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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description:
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Per-channel interrupt. Only necessary if no controller interrupt has
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been provided.
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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dma@100300 {
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compatible = "fsl,elo3-dma";
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reg = <0x100300 0x4>,
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<0x100600 0x4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x100100 0x500>;
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dma-channel@0 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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interrupts = <28 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@80 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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interrupts = <29 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@100 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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interrupts = <30 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@180 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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interrupts = <31 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@300 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x300 0x80>;
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interrupts = <76 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@380 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x380 0x80>;
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interrupts = <77 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@400 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x400 0x80>;
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interrupts = <78 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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dma-channel@480 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x480 0x80>;
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interrupts = <79 IRQ_TYPE_EDGE_FALLING 0 0>;
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};
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};
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...
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132
Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
Normal file
132
Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml
Normal file
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@ -0,0 +1,132 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale EloPlus DMA Controller
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maintainers:
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- J. Neuschäfer <j.ne@posteo.net>
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description:
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This is a 4-channel DMA controller with extended addresses and chaining,
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mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
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mpc8540, mpc8641 p4080, bsc9131 etc.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- fsl,mpc8540-dma
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- fsl,mpc8541-dma
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- fsl,mpc8548-dma
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- fsl,mpc8555-dma
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- fsl,mpc8560-dma
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- fsl,mpc8572-dma
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- fsl,mpc8641-dma
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- const: fsl,eloplus-dma
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- const: fsl,eloplus-dma
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reg:
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items:
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- description:
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DMA General Status Register, i.e. DGSR which contains
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status for all the 4 DMA channels
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000
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ranges: true
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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interrupts:
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maxItems: 1
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description: Controller interrupt.
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patternProperties:
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"^dma-channel@[0-9a-f]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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oneOf:
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# native DMA channel
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- items:
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- enum:
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- fsl,mpc8540-dma-channel
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- fsl,mpc8541-dma-channel
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- fsl,mpc8548-dma-channel
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- fsl,mpc8555-dma-channel
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- fsl,mpc8560-dma-channel
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- fsl,mpc8572-dma-channel
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- const: fsl,eloplus-dma-channel
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# audio DMA channel, see fsl,ssi.yaml
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- const: fsl,ssi-dma-channel
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reg:
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maxItems: 1
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cell-index:
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description: DMA channel index starts at 0.
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interrupts:
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maxItems: 1
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description:
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Per-channel interrupt. Only necessary if no controller interrupt has
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been provided.
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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dma@21300 {
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compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
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reg = <0x21300 4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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...
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@ -1,204 +0,0 @@
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* Freescale DMA Controllers
|
||||
|
||||
** Freescale Elo DMA Controller
|
||||
This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
|
||||
series chips such as mpc8315, mpc8349, mpc8379 etc.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : must include "fsl,elo-dma"
|
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- reg : DMA General Status Register, i.e. DGSR which contains
|
||||
status for all the 4 DMA channels
|
||||
- ranges : describes the mapping between the address space of the
|
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DMA channels and the address space of the DMA controller
|
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- cell-index : controller index. 0 for controller @ 0x8100
|
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- interrupts : interrupt specifier for DMA IRQ
|
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|
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- DMA channel nodes:
|
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- compatible : must include "fsl,elo-dma-channel"
|
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However, see note below.
|
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- reg : DMA channel specific registers
|
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- cell-index : DMA channel index starts at 0.
|
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|
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Optional properties:
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- interrupts : interrupt specifier for DMA channel IRQ
|
||||
(on 83xx this is expected to be identical to
|
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the interrupts property of the parent node)
|
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|
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Example:
|
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dma@82a8 {
|
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#address-cells = <1>;
|
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#size-cells = <1>;
|
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compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a4>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
|
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <0>;
|
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reg = <0 0x80>;
|
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interrupt-parent = <&ipic>;
|
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <1>;
|
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reg = <0x80 0x80>;
|
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interrupt-parent = <&ipic>;
|
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interrupts = <71 8>;
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};
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dma-channel@100 {
|
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <2>;
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reg = <0x100 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
|
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dma-channel@180 {
|
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
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cell-index = <3>;
|
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reg = <0x180 0x80>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
** Freescale EloPlus DMA Controller
|
||||
This is a 4-channel DMA controller with extended addresses and chaining,
|
||||
mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
|
||||
mpc8540, mpc8641 p4080, bsc9131 etc.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : must include "fsl,eloplus-dma"
|
||||
- reg : DMA General Status Register, i.e. DGSR which contains
|
||||
status for all the 4 DMA channels
|
||||
- cell-index : controller index. 0 for controller @ 0x21000,
|
||||
1 for controller @ 0xc000
|
||||
- ranges : describes the mapping between the address space of the
|
||||
DMA channels and the address space of the DMA controller
|
||||
|
||||
- DMA channel nodes:
|
||||
- compatible : must include "fsl,eloplus-dma-channel"
|
||||
However, see note below.
|
||||
- cell-index : DMA channel index starts at 0.
|
||||
- reg : DMA channel specific registers
|
||||
- interrupts : interrupt specifier for DMA channel IRQ
|
||||
|
||||
Example:
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 4>;
|
||||
ranges = <0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
** Freescale Elo3 DMA Controller
|
||||
DMA controller which has same function as EloPlus except that Elo3 has 8
|
||||
channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
|
||||
series chips, such as t1040, t4240, b4860.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : must include "fsl,elo3-dma"
|
||||
- reg : contains two entries for DMA General Status Registers,
|
||||
i.e. DGSR0 which includes status for channel 1~4, and
|
||||
DGSR1 for channel 5~8
|
||||
- ranges : describes the mapping between the address space of the
|
||||
DMA channels and the address space of the DMA controller
|
||||
|
||||
- DMA channel nodes:
|
||||
- compatible : must include "fsl,eloplus-dma-channel"
|
||||
- reg : DMA channel specific registers
|
||||
- interrupts : interrupt specifier for DMA channel IRQ
|
||||
|
||||
Example:
|
||||
dma@100300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elo3-dma";
|
||||
reg = <0x100300 0x4>,
|
||||
<0x100600 0x4>;
|
||||
ranges = <0x0 0x100100 0x500>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
interrupts = <28 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <29 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupts = <30 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
interrupts = <31 2 0 0>;
|
||||
};
|
||||
dma-channel@300 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x300 0x80>;
|
||||
interrupts = <76 2 0 0>;
|
||||
};
|
||||
dma-channel@380 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x380 0x80>;
|
||||
interrupts = <77 2 0 0>;
|
||||
};
|
||||
dma-channel@400 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x400 0x80>;
|
||||
interrupts = <78 2 0 0>;
|
||||
};
|
||||
dma-channel@480 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x480 0x80>;
|
||||
interrupts = <79 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
Note on DMA channel compatible properties: The compatible property must say
|
||||
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
|
||||
driver (fsldma). Any DMA channel used by fsldma cannot be used by another
|
||||
DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
|
||||
channel that should be used for another driver should not use
|
||||
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
|
||||
example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
|
||||
for more information.
|
||||
Loading…
Reference in New Issue
Block a user