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dt-bindings: PCI: ti,am65: Convert PCIe host/endpoint mode dt-bindings to YAML
Convert PCIe host/endpoint mode dt-bindings for TI's AM65/Keystone SoC to YAML binding. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210603133450.24710-1-kishon@ti.com Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Kishon Vijay Abraham I
Rob Herring
parent
0e407a9a29
commit
1fc4f5238d
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TI Keystone PCIe interface
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Keystone PCI host Controller is based on the Synopsys DesignWare PCI
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hardware version 3.65. It shares common functions with the PCIe DesignWare
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core driver and inherits common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt
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Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
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for the details of DesignWare DT bindings. Additional properties are
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described here as well as properties that are not applicable.
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Required Properties:-
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compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
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Should be "ti,am654-pcie-rc" for RC on AM654x SoC
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reg: Three register ranges as listed in the reg-names property
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reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
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TI specific application registers, "config" for the
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configuration space address
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pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
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interrupt-cells: should be set to 1
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interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
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(required if the compatible is "ti,keystone-pcie")
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msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
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(required if the compatible is "ti,am654-pcie-rc".
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ti,syscon-pcie-id : phandle to the device control module required to set device
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id and vendor id.
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ti,syscon-pcie-mode : phandle to the device control module required to configure
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PCI in either RC mode or EP mode.
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Example:
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pcie_msi_intc: msi-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
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};
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pcie_intc: Interrupt controller device node for Legacy IRQ chip
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interrupt-cells: should be set to 1
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Example:
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
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};
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Optional properties:-
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phys: phandle to generic Keystone SerDes PHY for PCI
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phy-names: name of the generic Keystone SerDes PHY for PCI
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- If boot loader already does PCI link establishment, then phys and
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phy-names shouldn't be present.
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interrupts: platform interrupt for error interrupts.
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DesignWare DT Properties not applicable for Keystone PCI
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1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
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AM654 PCIe Endpoint
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===================
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Required Properties:-
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compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC
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reg: Four register ranges as listed in the reg-names property
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reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
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TI specific application registers, "atu" for the
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Address Translation Unit configuration registers and
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"addr_space" used to map remote RC address space
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num-ib-windows: As specified in
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Documentation/devicetree/bindings/pci/designware-pcie.txt
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num-ob-windows: As specified in
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Documentation/devicetree/bindings/pci/designware-pcie.txt
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num-lanes: As specified in
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Documentation/devicetree/bindings/pci/designware-pcie.txt
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power-domains: As documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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ti,syscon-pcie-mode: phandle to the device control module required to configure
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PCI in either RC mode or EP mode.
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Optional properties:-
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phys: list of PHY specifiers (used by generic PHY framework)
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phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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number of lanes as specified in *num-lanes* property.
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("phys" and "phy-names" DT bindings are specified in
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Documentation/devicetree/bindings/phy/phy-bindings.txt)
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interrupts: platform interrupt for error interrupts.
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pcie-ep {
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compatible = "ti,am654-pcie-ep";
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reg = <0x5500000 0x1000>, <0x5501000 0x1000>,
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<0x10000000 0x8000000>, <0x5506000 0x1000>;
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reg-names = "app", "dbics", "addr_space", "atu";
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power-domains = <&k3_pds 120>;
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ti,syscon-pcie-mode = <&pcie0_mode>;
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num-lanes = <1>;
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num-ib-windows = <16>;
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num-ob-windows = <16>;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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};
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74
Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
Normal file
74
Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI AM65 PCI Endpoint
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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allOf:
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- $ref: pci-ep.yaml#
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properties:
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compatible:
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enum:
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- ti,am654-pcie-ep
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: app
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- const: dbics
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- const: addr_space
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- const: atu
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power-domains:
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maxItems: 1
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ti,syscon-pcie-mode:
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description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
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$ref: /schemas/types.yaml#/definitions/phandle
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interrupts:
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minItems: 1
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dma-coherent: true
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required:
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- compatible
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- reg
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- reg-names
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- max-link-speed
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- power-domains
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- ti,syscon-pcie-mode
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- dma-coherent
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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pcie0_ep: pcie-ep@5500000 {
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compatible = "ti,am654-pcie-ep";
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reg = <0x5500000 0x1000>,
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<0x5501000 0x1000>,
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<0x10000000 0x8000000>,
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<0x5506000 0x1000>;
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reg-names = "app", "dbics", "addr_space", "atu";
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power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
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ti,syscon-pcie-mode = <&pcie0_mode>;
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num-ib-windows = <16>;
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num-ob-windows = <16>;
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max-link-speed = <2>;
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dma-coherent;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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};
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96
Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
Normal file
96
Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
Normal file
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@ -0,0 +1,96 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI AM65 PCI Host
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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enum:
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- ti,am654-pcie-rc
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- ti,keystone-pcie
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: app
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- const: dbics
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- const: config
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- const: atu
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power-domains:
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maxItems: 1
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ti,syscon-pcie-id:
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description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
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$ref: /schemas/types.yaml#/definitions/phandle
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ti,syscon-pcie-mode:
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description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
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$ref: /schemas/types.yaml#/definitions/phandle
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msi-map: true
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dma-coherent: true
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required:
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- compatible
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- reg
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- reg-names
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- max-link-speed
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- ti,syscon-pcie-id
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- ti,syscon-pcie-mode
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- ranges
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if:
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properties:
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compatible:
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enum:
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- ti,am654-pcie-rc
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then:
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required:
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- dma-coherent
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- power-domains
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- msi-map
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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pcie0_rc: pcie@5500000 {
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compatible = "ti,am654-pcie-rc";
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reg = <0x5500000 0x1000>,
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<0x5501000 0x1000>,
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<0x10000000 0x2000>,
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<0x5506000 0x1000>;
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reg-names = "app", "dbics", "config", "atu";
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power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0x10020000 0 0x00010000>,
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<0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
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ti,syscon-pcie-id = <&pcie_devid>;
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ti,syscon-pcie-mode = <&pcie0_mode>;
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bus-range = <0x0 0xff>;
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num-viewport = <16>;
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max-link-speed = <2>;
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dma-coherent;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x0 0x10000>;
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device_type = "pci";
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};
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