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perf/x86: Remove swap_task_ctx()
The pmu specific data is saved in task_struct now. It doesn't need to swap between context. Remove swap_task_ctx() support. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20250314172700.438923-6-kan.liang@linux.intel.com
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@ -87,7 +87,6 @@ DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
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DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
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DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
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DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
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DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
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DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
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@ -2039,7 +2038,6 @@ static void x86_pmu_static_call_update(void)
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static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
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static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
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static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
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static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
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static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
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@ -2644,12 +2642,6 @@ static void x86_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
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static_call_cond(x86_pmu_sched_task)(pmu_ctx, task, sched_in);
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}
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static void x86_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
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struct perf_event_pmu_context *next_epc)
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{
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static_call_cond(x86_pmu_swap_task_ctx)(prev_epc, next_epc);
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}
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void perf_check_microcode(void)
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{
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if (x86_pmu.check_microcode)
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@ -2714,7 +2706,6 @@ static struct pmu pmu = {
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.event_idx = x86_pmu_event_idx,
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.sched_task = x86_pmu_sched_task,
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.swap_task_ctx = x86_pmu_swap_task_ctx,
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.check_period = x86_pmu_check_period,
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.aux_output_match = x86_pmu_aux_output_match,
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@ -5300,12 +5300,6 @@ static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
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intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in);
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}
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static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
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struct perf_event_pmu_context *next_epc)
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{
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intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc);
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}
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static int intel_pmu_check_period(struct perf_event *event, u64 value)
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{
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return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
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@ -5474,7 +5468,6 @@ static __initconst const struct x86_pmu intel_pmu = {
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.guest_get_msrs = intel_guest_get_msrs,
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.sched_task = intel_pmu_sched_task,
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.swap_task_ctx = intel_pmu_swap_task_ctx,
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.check_period = intel_pmu_check_period,
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@ -522,29 +522,6 @@ static void __intel_pmu_lbr_save(void *ctx)
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cpuc->last_log_id = ++task_context_opt(ctx)->log_id;
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}
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void intel_pmu_lbr_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
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struct perf_event_pmu_context *next_epc)
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{
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void *prev_ctx_data, *next_ctx_data;
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swap(prev_epc->task_ctx_data, next_epc->task_ctx_data);
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/*
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* Architecture specific synchronization makes sense in case
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* both prev_epc->task_ctx_data and next_epc->task_ctx_data
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* pointers are allocated.
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*/
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prev_ctx_data = next_epc->task_ctx_data;
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next_ctx_data = prev_epc->task_ctx_data;
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if (!prev_ctx_data || !next_ctx_data)
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return;
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swap(task_context_opt(prev_ctx_data)->lbr_callstack_users,
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task_context_opt(next_ctx_data)->lbr_callstack_users);
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}
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void intel_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx,
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struct task_struct *task, bool sched_in)
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{
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@ -958,14 +958,6 @@ struct x86_pmu {
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*/
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int num_topdown_events;
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/*
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* perf task context (i.e. struct perf_event_pmu_context::task_ctx_data)
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* switch helper to bridge calls from perf/core to perf/x86.
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* See struct pmu::swap_task_ctx() usage for examples;
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*/
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void (*swap_task_ctx)(struct perf_event_pmu_context *prev_epc,
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struct perf_event_pmu_context *next_epc);
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/*
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* AMD bits
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*/
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@ -1671,9 +1663,6 @@ void intel_pmu_lbr_save_brstack(struct perf_sample_data *data,
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struct cpu_hw_events *cpuc,
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struct perf_event *event);
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void intel_pmu_lbr_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
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struct perf_event_pmu_context *next_epc);
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void intel_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx,
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struct task_struct *task, bool sched_in);
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