From 1fac72873549bbdd6292014d9676bcf1c39cf285 Mon Sep 17 00:00:00 2001 From: Aravind Anilraj Date: Sun, 29 Mar 2026 03:06:41 -0400 Subject: [PATCH] thermal: intel: int340x: Fix potential shift overflow in ptc_mmio_write() The value parameter is u32 but is shifted into a u64 register value without casting first. If the shift amount pushes bits beyond 32, they are lost. Cast value to u64 before shifting to ensure all bits are preserved. Signed-off-by: Aravind Anilraj Link: https://patch.msgid.link/20260329070642.10721-2-aravindanilraj0702@gmail.com Signed-off-by: Rafael J. Wysocki --- .../intel/int340x_thermal/platform_temperature_control.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c b/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c index 0ccc72c93499..18ac5014d8dc 100644 --- a/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c +++ b/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c @@ -138,7 +138,7 @@ static void ptc_mmio_write(struct pci_dev *pdev, u32 offset, int index, u32 valu reg_val = readq((void __iomem *) (proc_priv->mmio_base + offset)); reg_val &= ~mask; - reg_val |= (value << ptc_mmio_regs[index].shift); + reg_val |= ((u64)value << ptc_mmio_regs[index].shift); writeq(reg_val, (void __iomem *) (proc_priv->mmio_base + offset)); }