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arm64: dts: ti: k3-j721s2: Change CPTS clock parent

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MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's
capability to re-initialise clock frequencies. CPTS and RGMII has
MAIN_PLL3 as their parent which does not have this flag. While RGMII
needs this reinitialisation to default frequency to be able to get
250MHz with its divider, CPTS can not get its required 200MHz with its
divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to
MAIN_PLL0_HSDIV6.

(Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side
for the same reason)

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20230605110443.84568-1-n-francis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Neha Malcom Francis 2023-06-05 16:34:43 +05:30 committed by Vignesh Raghavendra
parent 74428680d7
commit 1f36d0e8be
2 changed files with 4 additions and 0 deletions
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2
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
View File

@ -1030,6 +1030,8 @@ cpts@310d0000 {
reg-names = "cpts";
clocks = <&k3_clks 226 5>;
clock-names = "cpts";
assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;

2
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
View File

@ -525,6 +525,8 @@ cpts@3d000 {
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 29 3>;
clock-names = "cpts";
assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;