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drm/msm/a6xx: Sync latest register definitions
Sync the latest register definitions from Mesa which includes the updates for A8x family. Co-developed-by: Rob Clark <robin.clark@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689009/ Message-ID: <20251118-kaana-gpu-support-v4-9-86eeb8e93fb6@oss.qualcomm.com>
This commit is contained in:
Akhil P Oommen
Rob Clark
parent
0d9f5ee458
commit
1ef05ef9fa
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@ -201,6 +201,7 @@ ADRENO_HEADERS = \
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generated/a6xx_perfcntrs.xml.h \
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generated/a7xx_enums.xml.h \
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generated/a7xx_perfcntrs.xml.h \
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generated/a8xx_enums.xml.h \
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generated/a6xx_gmu.xml.h \
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generated/adreno_common.xml.h \
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generated/adreno_pm4.xml.h \
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@ -238,7 +238,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
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OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH);
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, LRZ_FLUSH);
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OUT_RING(ring, LRZ_FLUSH_INVALIDATE);
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OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
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OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);
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@ -381,7 +381,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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rbmemptr_stats(ring, index, alwayson_end));
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/* Write the fence to the scratch register */
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OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
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OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1);
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OUT_RING(ring, submit->seqno);
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/*
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@ -522,7 +522,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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rbmemptr_stats(ring, index, alwayson_end));
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/* Write the fence to the scratch register */
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OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
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OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1);
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OUT_RING(ring, submit->seqno);
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OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
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@ -1305,7 +1305,7 @@ static int hw_init(struct msm_gpu *gpu)
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}
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if (adreno_is_a660_family(adreno_gpu))
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gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
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gpu_write(gpu, REG_A7XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
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/* Setting the mem pool size */
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if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) {
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@ -1754,10 +1754,10 @@ static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *da
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const char *block = "unknown";
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u32 scratch[] = {
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gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
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gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
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gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
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gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)),
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gpu_read(gpu, REG_A6XX_CP_SCRATCH(4)),
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gpu_read(gpu, REG_A6XX_CP_SCRATCH(5)),
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gpu_read(gpu, REG_A6XX_CP_SCRATCH(6)),
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gpu_read(gpu, REG_A6XX_CP_SCRATCH(7)),
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};
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if (info)
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@ -71,8 +71,8 @@ static const struct a6xx_cluster {
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u32 sel_val;
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} a6xx_clusters[] = {
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CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0),
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CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
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CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
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CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
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CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
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CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0),
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CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0),
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CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0),
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@ -303,8 +303,8 @@ static const u32 a660_registers[] = {
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static const struct a6xx_registers a6xx_reglist[] = {
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REGS(a6xx_registers, 0, 0),
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REGS(a660_registers, 0, 0),
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REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
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REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
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REGS(a6xx_rb_rac_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
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REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
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};
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static const u32 a6xx_ahb_registers[] = {
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@ -691,14 +691,14 @@ static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = {
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static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8));
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static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = {
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.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
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.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
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.val = 0x0,
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};
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static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = {
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.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
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.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
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.val = 0x9,
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};
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@ -478,14 +478,14 @@ static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = {
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static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8));
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static const struct gen7_sel_reg gen7_2_0_rb_rac_sel = {
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.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
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.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
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.val = 0x0,
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};
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static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = {
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.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
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.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
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.val = 0x9,
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};
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@ -1105,14 +1105,14 @@ static const u32 gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers[] = {
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static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers), 8));
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static const struct gen7_sel_reg gen7_9_0_rb_rac_sel = {
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.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
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.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
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.val = 0,
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};
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static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = {
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.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
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.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
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.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
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.val = 0x9,
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};
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File diff suppressed because it is too large
Load Diff
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@ -303,7 +303,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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</enum>
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<!--
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Used in a6xx_a2d_bit_cntl.. the value mostly seems to correlate to the
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Used in a6xx_a2d_blt_cntl.. the value mostly seems to correlate to the
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component type/size, so I think it relates to internal format used for
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blending? The one exception is that 16b unorm and 32b float use the
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same value... maybe 16b unorm is uncommon enough that it was just easier
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121
drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml
Normal file
121
drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml
Normal file
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@ -0,0 +1,121 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<database xmlns="http://nouveau.freedesktop.org/"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<import file="freedreno_copyright.xml"/>
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<import file="adreno/adreno_common.xml"/>
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<import file="adreno/adreno_pm4.xml"/>
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<import file="adreno/a6xx_enums.xml"/>
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<import file="adreno/a8xx_enums.xml"/>
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<domain name="A8XX_TEX_SAMP" width="32">
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<doc>Texture sampler dwords</doc>
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<reg32 offset="0" name="0">
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<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
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<bitfield name="MIPMAPING_DIS" pos="1" type="boolean"/>
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<bitfield name="XY_MAG" low="2" high="3" type="a6xx_tex_filter"/>
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<bitfield name="XY_MIN" low="4" high="5" type="a6xx_tex_filter"/>
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<bitfield name="WRAP_S" low="6" high="8" type="a6xx_tex_clamp"/>
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<bitfield name="WRAP_T" low="9" high="11" type="a6xx_tex_clamp"/>
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<bitfield name="WRAP_R" low="12" high="14" type="a6xx_tex_clamp"/>
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<bitfield name="MSAA_BOX_FILTERING" pos="15" type="boolean"/>
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<bitfield name="LOD_BIAS" low="16" high="28" type="fixed" radix="8"/>
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<bitfield name="ANISO" low="29" high="31" type="a6xx_tex_aniso"/>
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</reg32>
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<reg32 offset="1" name="1">
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<bitfield name="MAX_LOD" low="0" high="11" type="ufixed" radix="8"/>
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<bitfield name="MIN_LOD" low="12" high="23" type="ufixed" radix="8"/>
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<bitfield name="REDUCTION_MODE" low="24" high="25" type="a6xx_reduction_mode"/>
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<bitfield name="COMPARE_FUNC" low="26" high="28" type="adreno_compare_func"/>
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<bitfield name="CHROMA_LINEAR" pos="29" type="boolean"/>
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<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="30" type="boolean"/>
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<bitfield name="UNNORM_COORDS" pos="31" type="boolean"/>
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</reg32>
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<reg32 offset="2" name="2">
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<bitfield name="FASTBORDERCOLOREN" pos="0" type="boolean"/>
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<bitfield name="FASTBORDERCOLOR" low="1" high="2" type="a6xx_fast_border_color"/>
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<bitfield name="BCOLOR" low="7" high="31"/>
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</reg32>
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<reg32 offset="3" name="3"/>
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</domain>
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<domain name="A8XX_TEX_MEMOBJ" width="32" varset="chip">
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<doc>Texture memobj dwords</doc>
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<reg32 offset="0" name="0">
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<bitfield name="BASE_LO" low="6" high="31" shr="6"/>
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</reg32>
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<reg32 offset="1" name="1">
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<bitfield name="BASE_HI" low="0" high="16"/>
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<bitfield name="TYPE" low="17" high="19" type="a6xx_tex_type"/>
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<bitfield name="DEPTH" low="20" high="31" type="uint"/>
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</reg32>
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<reg32 offset="2" name="2">
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<bitfield name="WIDTH" low="0" high="14" type="uint"/>
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<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
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<bitfield name="SAMPLES" low="30" high="31" type="a3xx_msaa_samples"/>
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</reg32>
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<reg32 offset="3" name="3">
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<bitfield name="FMT" low="0" high="7" type="a6xx_format"/>
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<bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
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<bitfield name="SWIZ_X" low="10" high="12" type="a8xx_tex_swiz"/>
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<bitfield name="SWIZ_Y" low="13" high="15" type="a8xx_tex_swiz"/>
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<bitfield name="SWIZ_Z" low="16" high="18" type="a8xx_tex_swiz"/>
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<bitfield name="SWIZ_W" low="19" high="21" type="a8xx_tex_swiz"/>
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</reg32>
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<reg32 offset="4" name="4">
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<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
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<bitfield name="FLAG" pos="2" type="boolean"/>
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<bitfield name="PRT_EN" pos="3" type="boolean"/>
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<bitfield name="TILE_ALL" pos="4" type="boolean"/>
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<bitfield name="SRGB" pos="5" type="boolean"/>
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<bitfield name="FLAG_LO" low="6" high="31" shr="6"/>
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<!-- For multiplanar: -->
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<bitfield name="BASE_U_LO" low="6" high="31" shr="6"/>
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</reg32>
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<reg32 offset="5" name="5">
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<bitfield name="FLAG_HI" low="0" high="16"/>
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<!-- For multiplanar: -->
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<bitfield name="BASE_U_HI" low="0" high="16"/>
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<bitfield name="FLAG_BUFFER_PITCH" low="17" high="24" shr="6" type="uint"/>
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<bitfield name="ALL_SAMPLES_CENTER" pos="29" type="boolean"/>
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<bitfield name="MUTABLEEN" pos="31" type="boolean"/>
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</reg32>
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<reg32 offset="6" name="6">
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<bitfield name="TEX_LINE_OFFSET" low="0" high="23" type="uint"/> <!-- PITCH -->
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<bitfield name="MIN_LINE_OFFSET" low="24" high="27" type="uint"/> <!-- PITCHALIGN -->
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<bitfield name="MIPLVLS" low="28" high="31" type="uint"/>
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</reg32>
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<reg32 offset="7" name="7">
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<bitfield name="ARRAY_SLICE_OFFSET" low="0" high="22" shr="12" type="uint"/> <!-- ARRAY_PITCH -->
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<bitfield name="ASO_UNIT" pos="23"/> <!-- 4KB or 32B ? -->
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<bitfield name="MIN_ARRAY_SLIZE_OFFSET" low="24" high="27" shr="12"/> <!-- MIN_LAYERSZ -->
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<bitfield name="GMEM_TILING_FALLBACK_EN" pos="28" type="boolean"/>
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<bitfield name="CORNER_BASED_EN" pos="30" type="boolean"/>
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<bitfield name="GMEM_FULL_SURF" pos="31" type="boolean"/>
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<!-- For multiplanar. This overlaps other single-planar fields: -->
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<bitfield name="UV_OFFSET_H" low="24" high="25" type="ufixed" radix="2"/> <!-- CHROMA_MIDPOINT_X -->
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<bitfield name="UV_OFFSET_V" low="26" high="27" type="ufixed" radix="2"/> <!-- CHROMA_MIDPOINT_Y -->
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</reg32>
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<reg32 offset="8" name="8">
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<bitfield name="FLAG_ARRAY_PITCH" low="0" high="14" shr="12" type="uint"/> <!-- FLAG_BUFFER_ARRAY_PITCH -->
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<!-- log2 size of the first level, required for mipmapping -->
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<bitfield name="FLAG_BUFFER_LOGW" low="24" high="27" type="uint"/>
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<bitfield name="FLAG_BUFFER_LOGH" low="28" high="31" type="uint"/>
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<!-- For multiplanar. This overlaps other single-planar fields: -->
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<bitfield name="BASE_V_LO" low="6" high="31" shr="6"/>
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</reg32>
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<reg32 offset="9" name="9">
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<bitfield name="MIN_LOD_CLAMP" low="19" high="30" type="ufixed" radix="8"/>
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<!-- For multiplanar, this overlaps other fields: -->
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<bitfield name="BASE_V_HI" low="0" high="16"/>
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<bitfield name="UV_PITCH" low="17" high="26"/> <!-- PLANE_PITCH -->
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</reg32>
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<reg32 offset="10" name="10"/>
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<reg32 offset="11" name="11"/>
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<reg32 offset="12" name="12"/>
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<reg32 offset="13" name="13"/>
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<reg32 offset="14" name="14"/>
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<reg32 offset="15" name="15"/>
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</domain>
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</database>
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299
drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml
Normal file
299
drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml
Normal file
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@ -0,0 +1,299 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<database xmlns="http://nouveau.freedesktop.org/"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<import file="freedreno_copyright.xml"/>
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<import file="adreno/adreno_common.xml"/>
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<import file="adreno/adreno_pm4.xml"/>
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<enum name="a8xx_statetype_id">
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<value value="0" name="A8XX_TP0_NCTX_REG"/>
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<value value="1" name="A8XX_TP0_CTX0_3D_CVS_REG"/>
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<value value="2" name="A8XX_TP0_CTX0_3D_CPS_REG"/>
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<value value="3" name="A8XX_TP0_CTX1_3D_CVS_REG"/>
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<value value="4" name="A8XX_TP0_CTX1_3D_CPS_REG"/>
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<value value="5" name="A8XX_TP0_CTX2_3D_CPS_REG"/>
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<value value="6" name="A8XX_TP0_CTX3_3D_CPS_REG"/>
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<value value="9" name="A8XX_TP0_TMO_DATA"/>
|
||||
<value value="10" name="A8XX_TP0_SMO_DATA"/>
|
||||
<value value="11" name="A8XX_TP0_MIPMAP_BASE_DATA"/>
|
||||
<value value="12" name="A8XX_TP_3D_CVS_REG"/>
|
||||
<value value="13" name="A8XX_TP_3D_CPS_REG"/>
|
||||
<value value="16" name="A8XX_SP_3D_CVS_REG"/>
|
||||
<value value="17" name="A8XX_SP_3D_CPS_REG"/>
|
||||
<value value="22" name="A8XX_SP_LB_DATA_RAM"/>
|
||||
<value value="23" name="A8XX_SP_INST_DATA_RAM"/>
|
||||
<value value="24" name="A8XX_SP_STH"/>
|
||||
<value value="25" name="A8XX_SP_EVQ"/>
|
||||
<value value="26" name="A8XX_SP_CONSMNG"/>
|
||||
<value value="30" name="A8XX_HLSQ_INST_DATA_RAM"/>
|
||||
<value value="31" name="A8XX_SP_INST_DATA_3"/>
|
||||
<value value="32" name="A8XX_SP_NCTX_REG"/>
|
||||
<value value="33" name="A8XX_SP_CTX0_3D_CVS_REG"/>
|
||||
<value value="34" name="A8XX_SP_CTX0_3D_CPS_REG"/>
|
||||
<value value="35" name="A8XX_SP_CTX1_3D_CVS_REG"/>
|
||||
<value value="36" name="A8XX_SP_CTX1_3D_CPS_REG"/>
|
||||
<value value="37" name="A8XX_SP_CTX2_3D_CPS_REG"/>
|
||||
<value value="38" name="A8XX_SP_CTX3_3D_CPS_REG"/>
|
||||
<value value="39" name="A8XX_SP_INST_DATA"/>
|
||||
<value value="40" name="A8XX_SP_INST_DATA_1"/>
|
||||
<value value="41" name="A8XX_SP_LB_0_DATA"/>
|
||||
<value value="42" name="A8XX_SP_LB_1_DATA"/>
|
||||
<value value="43" name="A8XX_SP_LB_2_DATA"/>
|
||||
<value value="44" name="A8XX_SP_LB_3_DATA"/>
|
||||
<value value="45" name="A8XX_SP_LB_4_DATA"/>
|
||||
<value value="46" name="A8XX_SP_LB_5_DATA"/>
|
||||
<value value="47" name="A8XX_SP_LB_6_DATA"/>
|
||||
<value value="48" name="A8XX_SP_LB_7_DATA"/>
|
||||
<value value="49" name="A8XX_SP_CB_RAM"/>
|
||||
<value value="50" name="A8XX_SP_LB_13_DATA"/>
|
||||
<value value="51" name="A8XX_SP_LB_14_DATA"/>
|
||||
<value value="52" name="A8XX_SP_INST_TAG"/>
|
||||
<value value="53" name="A8XX_SP_INST_DATA_2"/>
|
||||
<value value="54" name="A8XX_SP_TMO_TAG"/>
|
||||
<value value="55" name="A8XX_SP_SMO_TAG"/>
|
||||
<value value="56" name="A8XX_SP_STATE_DATA"/>
|
||||
<value value="57" name="A8XX_SP_HWAVE_RAM"/>
|
||||
<value value="58" name="A8XX_SP_L0_INST_BUF"/>
|
||||
<value value="59" name="A8XX_SP_LB_8_DATA"/>
|
||||
<value value="60" name="A8XX_SP_LB_9_DATA"/>
|
||||
<value value="61" name="A8XX_SP_LB_10_DATA"/>
|
||||
<value value="62" name="A8XX_SP_LB_11_DATA"/>
|
||||
<value value="63" name="A8XX_SP_LB_12_DATA"/>
|
||||
<value value="64" name="A8XX_HLSQ_DATAPATH_DSTR_META"/>
|
||||
<value value="65" name="A8XX_HLSQ_DESC_REMAP_META"/>
|
||||
<value value="66" name="A8XX_HLSQ_SLICE_TOP_META"/>
|
||||
<value value="67" name="A8XX_HLSQ_L2STC_TAG_RAM"/>
|
||||
<value value="68" name="A8XX_HLSQ_L2STC_INFO_CMD"/>
|
||||
<value value="69" name="A8XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/>
|
||||
<value value="70" name="A8XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/>
|
||||
<value value="71" name="A8XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/>
|
||||
<value value="72" name="A8XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/>
|
||||
<value value="73" name="A8XX_HLSQ_CHUNK_CVS_RAM"/>
|
||||
<value value="74" name="A8XX_HLSQ_CHUNK_CPS_RAM"/>
|
||||
<value value="75" name="A8XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
|
||||
<value value="76" name="A8XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
|
||||
<value value="77" name="A8XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
|
||||
<value value="78" name="A8XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
|
||||
<value value="79" name="A8XX_HLSQ_CVS_MISC_RAM"/>
|
||||
<value value="80" name="A8XX_HLSQ_CPS_MISC_RAM"/>
|
||||
<value value="81" name="A8XX_HLSQ_CPS_MISC_RAM_1"/>
|
||||
<value value="82" name="A8XX_HLSQ_INST_RAM"/>
|
||||
<value value="83" name="A8XX_HLSQ_GFX_CVS_CONST_RAM"/>
|
||||
<value value="84" name="A8XX_HLSQ_GFX_CPS_CONST_RAM"/>
|
||||
<value value="85" name="A8XX_HLSQ_CVS_MISC_RAM_TAG"/>
|
||||
<value value="86" name="A8XX_HLSQ_CPS_MISC_RAM_TAG"/>
|
||||
<value value="87" name="A8XX_HLSQ_INST_RAM_TAG"/>
|
||||
<value value="88" name="A8XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
|
||||
<value value="89" name="A8XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
|
||||
<value value="90" name="A8XX_HLSQ_GFX_LOCAL_MISC_RAM"/>
|
||||
<value value="91" name="A8XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/>
|
||||
<value value="92" name="A8XX_HLSQ_INST_RAM_1"/>
|
||||
<value value="93" name="A8XX_HLSQ_STPROC_META"/>
|
||||
<value value="94" name="A8XX_HLSQ_SLICE_BACKEND_META"/>
|
||||
<value value="95" name="A8XX_HLSQ_INST_RAM_2"/>
|
||||
<value value="96" name="A8XX_HLSQ_DATAPATH_META"/>
|
||||
<value value="97" name="A8XX_HLSQ_FRONTEND_META"/>
|
||||
<value value="98" name="A8XX_HLSQ_INDIRECT_META"/>
|
||||
<value value="99" name="A8XX_HLSQ_BACKEND_META"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a8xx_state_location">
|
||||
<value value="0" name="A8XX_HLSQ_STATE"/>
|
||||
<value value="1" name="A8XX_HLSQ_DP"/>
|
||||
<value value="2" name="A8XX_SP_TOP"/>
|
||||
<value value="3" name="A8XX_USPTP"/>
|
||||
<value value="4" name="A8XX_HLSQ_DP_STR"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a8xx_cluster">
|
||||
<value value="0" name="A8XX_CLUSTER_NONE"/>
|
||||
<value value="1" name="A8XX_CLUSTER_FE_US"/>
|
||||
<value value="2" name="A8XX_CLUSTER_FE_S"/>
|
||||
<value value="3" name="A8XX_CLUSTER_SP_VS"/>
|
||||
<value value="4" name="A8XX_CLUSTER_VPC_VS"/>
|
||||
<value value="5" name="A8XX_CLUSTER_VPC_US"/>
|
||||
<value value="6" name="A8XX_CLUSTER_GRAS"/>
|
||||
<value value="7" name="A8XX_CLUSTER_SP_PS"/>
|
||||
<value value="8" name="A8XX_CLUSTER_VPC_PS"/>
|
||||
<value value="9" name="A8XX_CLUSTER_PS"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a8xx_debugbus_id">
|
||||
<value value="1" name="A8XX_DEBUGBUS_GBIF_CX_GC_US_I_0"/>
|
||||
<value value="2" name="A8XX_DEBUGBUS_GMU_CX_GC_US_I_0"/>
|
||||
<value value="3" name="A8XX_DEBUGBUS_CX_GC_US_I_0"/>
|
||||
<value value="8" name="A8XX_DEBUGBUS_GBIF_GX_GC_US_I_0"/>
|
||||
<value value="9" name="A8XX_DEBUGBUS_GMU_GX_GC_US_I_0"/>
|
||||
<value value="10" name="A8XX_DEBUGBUS_DBGC_GC_US_I_0"/>
|
||||
<value value="11" name="A8XX_DEBUGBUS_RBBM_GC_US_I_0"/>
|
||||
<value value="12" name="A8XX_DEBUGBUS_LARC_GC_US_I_0"/>
|
||||
<value value="13" name="A8XX_DEBUGBUS_COM_GC_US_I_0"/>
|
||||
<value value="14" name="A8XX_DEBUGBUS_HLSQ_GC_US_I_0"/>
|
||||
<value value="15" name="A8XX_DEBUGBUS_CGC_GC_US_I_0"/>
|
||||
<value value="20" name="A8XX_DEBUGBUS_VSC_GC_US_I_0_0"/>
|
||||
<value value="21" name="A8XX_DEBUGBUS_VSC_GC_US_I_0_1"/>
|
||||
<value value="24" name="A8XX_DEBUGBUS_UFC_GC_US_I_0"/>
|
||||
<value value="25" name="A8XX_DEBUGBUS_UFC_GC_US_I_1"/>
|
||||
<value value="40" name="A8XX_DEBUGBUS_CP_GC_US_I_0_0"/>
|
||||
<value value="41" name="A8XX_DEBUGBUS_CP_GC_US_I_0_1"/>
|
||||
<value value="42" name="A8XX_DEBUGBUS_CP_GC_US_I_0_2"/>
|
||||
<value value="56" name="A8XX_DEBUGBUS_PC_BR_US_I_0"/>
|
||||
<value value="57" name="A8XX_DEBUGBUS_PC_BV_US_I_0"/>
|
||||
<value value="58" name="A8XX_DEBUGBUS_GPC_BR_US_I_0"/>
|
||||
<value value="59" name="A8XX_DEBUGBUS_GPC_BV_US_I_0"/>
|
||||
<value value="60" name="A8XX_DEBUGBUS_VPC_BR_US_I_0"/>
|
||||
<value value="61" name="A8XX_DEBUGBUS_VPC_BV_US_I_0"/>
|
||||
<value value="80" name="A8XX_DEBUGBUS_UCHE_WRAPPER_GC_US_I_0"/>
|
||||
<value value="81" name="A8XX_DEBUGBUS_UCHE_GC_US_I_0"/>
|
||||
<value value="82" name="A8XX_DEBUGBUS_UCHE_GC_US_I_1"/>
|
||||
<value value="83" name="A8XX_DEBUGBUS_UCHE_GC_US_I_0_1"/>
|
||||
<value value="84" name="A8XX_DEBUGBUS_UCHE_GC_US_I_1_1"/>
|
||||
<value value="128" name="A8XX_DEBUGBUS_CP_GC_S_0_I_0"/>
|
||||
<value value="129" name="A8XX_DEBUGBUS_PC_BR_S_0_I_0"/>
|
||||
<value value="130" name="A8XX_DEBUGBUS_PC_BV_S_0_I_0"/>
|
||||
<value value="131" name="A8XX_DEBUGBUS_TESS_GC_S_0_I_0"/>
|
||||
<value value="132" name="A8XX_DEBUGBUS_TSEFE_GC_S_0_I_0"/>
|
||||
<value value="133" name="A8XX_DEBUGBUS_TSEBE_GC_S_0_I_0"/>
|
||||
<value value="134" name="A8XX_DEBUGBUS_RAS_GC_S_0_I_0"/>
|
||||
<value value="135" name="A8XX_DEBUGBUS_LRZ_BR_S_0_I_0"/>
|
||||
<value value="136" name="A8XX_DEBUGBUS_LRZ_BV_S_0_I_0"/>
|
||||
<value value="137" name="A8XX_DEBUGBUS_VFDP_GC_S_0_I_0"/>
|
||||
<value value="138" name="A8XX_DEBUGBUS_GPC_BR_S_0_I_0"/>
|
||||
<value value="139" name="A8XX_DEBUGBUS_GPC_BV_S_0_I_0"/>
|
||||
<value value="140" name="A8XX_DEBUGBUS_VPCFE_BR_S_0_I_0"/>
|
||||
<value value="141" name="A8XX_DEBUGBUS_VPCFE_BV_S_0_I_0"/>
|
||||
<value value="142" name="A8XX_DEBUGBUS_VPCBE_BR_S_0_I_0"/>
|
||||
<value value="143" name="A8XX_DEBUGBUS_VPCBE_BV_S_0_I_0"/>
|
||||
<value value="144" name="A8XX_DEBUGBUS_CCHE_GC_S_0_I_0"/>
|
||||
<value value="145" name="A8XX_DEBUGBUS_DBGC_GC_S_0_I_0"/>
|
||||
<value value="146" name="A8XX_DEBUGBUS_LARC_GC_S_0_I_0"/>
|
||||
<value value="147" name="A8XX_DEBUGBUS_RBBM_GC_S_0_I_0"/>
|
||||
<value value="148" name="A8XX_DEBUGBUS_CCRE_GC_S_0_I_0"/>
|
||||
<value value="149" name="A8XX_DEBUGBUS_CGC_GC_S_0_I_0"/>
|
||||
<value value="150" name="A8XX_DEBUGBUS_GMU_GC_S_0_I_0"/>
|
||||
<value value="151" name="A8XX_DEBUGBUS_SLICE_GC_S_0_I_0"/>
|
||||
<value value="152" name="A8XX_DEBUGBUS_HLSQ_SPTP_STAR_GC_S_0_I_0"/>
|
||||
<value value="160" name="A8XX_DEBUGBUS_USP_GC_S_0_I_0"/>
|
||||
<value value="161" name="A8XX_DEBUGBUS_USP_GC_S_0_I_1"/>
|
||||
<value value="166" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_0"/>
|
||||
<value value="167" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_1"/>
|
||||
<value value="168" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_2"/>
|
||||
<value value="169" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_3"/>
|
||||
<value value="178" name="A8XX_DEBUGBUS_TP_GC_S_0_I_0"/>
|
||||
<value value="179" name="A8XX_DEBUGBUS_TP_GC_S_0_I_1"/>
|
||||
<value value="180" name="A8XX_DEBUGBUS_TP_GC_S_0_I_2"/>
|
||||
<value value="181" name="A8XX_DEBUGBUS_TP_GC_S_0_I_3"/>
|
||||
<value value="190" name="A8XX_DEBUGBUS_RB_GC_S_0_I_0"/>
|
||||
<value value="191" name="A8XX_DEBUGBUS_RB_GC_S_0_I_1"/>
|
||||
<value value="196" name="A8XX_DEBUGBUS_CCU_GC_S_0_I_0"/>
|
||||
<value value="197" name="A8XX_DEBUGBUS_CCU_GC_S_0_I_1"/>
|
||||
<value value="202" name="A8XX_DEBUGBUS_HLSQ_GC_S_0_I_0"/>
|
||||
<value value="203" name="A8XX_DEBUGBUS_HLSQ_GC_S_0_I_1"/>
|
||||
<value value="208" name="A8XX_DEBUGBUS_VFD_GC_S_0_I_0"/>
|
||||
<value value="209" name="A8XX_DEBUGBUS_VFD_GC_S_0_I_1"/>
|
||||
<value value="256" name="A8XX_DEBUGBUS_CP_GC_S_1_I_0"/>
|
||||
<value value="257" name="A8XX_DEBUGBUS_PC_BR_S_1_I_0"/>
|
||||
<value value="258" name="A8XX_DEBUGBUS_PC_BV_S_1_I_0"/>
|
||||
<value value="259" name="A8XX_DEBUGBUS_TESS_GC_S_1_I_0"/>
|
||||
<value value="260" name="A8XX_DEBUGBUS_TSEFE_GC_S_1_I_0"/>
|
||||
<value value="261" name="A8XX_DEBUGBUS_TSEBE_GC_S_1_I_0"/>
|
||||
<value value="262" name="A8XX_DEBUGBUS_RAS_GC_S_1_I_0"/>
|
||||
<value value="263" name="A8XX_DEBUGBUS_LRZ_BR_S_1_I_0"/>
|
||||
<value value="264" name="A8XX_DEBUGBUS_LRZ_BV_S_1_I_0"/>
|
||||
<value value="265" name="A8XX_DEBUGBUS_VFDP_GC_S_1_I_0"/>
|
||||
<value value="266" name="A8XX_DEBUGBUS_GPC_BR_S_1_I_0"/>
|
||||
<value value="267" name="A8XX_DEBUGBUS_GPC_BV_S_1_I_0"/>
|
||||
<value value="268" name="A8XX_DEBUGBUS_VPCFE_BR_S_1_I_0"/>
|
||||
<value value="269" name="A8XX_DEBUGBUS_VPCFE_BV_S_1_I_0"/>
|
||||
<value value="270" name="A8XX_DEBUGBUS_VPCBE_BR_S_1_I_0"/>
|
||||
<value value="271" name="A8XX_DEBUGBUS_VPCBE_BV_S_1_I_0"/>
|
||||
<value value="272" name="A8XX_DEBUGBUS_CCHE_GC_S_1_I_0"/>
|
||||
<value value="273" name="A8XX_DEBUGBUS_DBGC_GC_S_1_I_0"/>
|
||||
<value value="274" name="A8XX_DEBUGBUS_LARC_GC_S_1_I_0"/>
|
||||
<value value="275" name="A8XX_DEBUGBUS_RBBM_GC_S_1_I_0"/>
|
||||
<value value="276" name="A8XX_DEBUGBUS_CCRE_GC_S_1_I_0"/>
|
||||
<value value="277" name="A8XX_DEBUGBUS_CGC_GC_S_1_I_0"/>
|
||||
<value value="278" name="A8XX_DEBUGBUS_GMU_GC_S_1_I_0"/>
|
||||
<value value="279" name="A8XX_DEBUGBUS_SLICE_GC_S_1_I_0"/>
|
||||
<value value="280" name="A8XX_DEBUGBUS_HLSQ_SPTP_STAR_GC_S_1_I_0"/>
|
||||
<value value="288" name="A8XX_DEBUGBUS_USP_GC_S_1_I_0"/>
|
||||
<value value="289" name="A8XX_DEBUGBUS_USP_GC_S_1_I_1"/>
|
||||
<value value="294" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_0"/>
|
||||
<value value="295" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_1"/>
|
||||
<value value="296" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_2"/>
|
||||
<value value="297" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_3"/>
|
||||
<value value="306" name="A8XX_DEBUGBUS_TP_GC_S_1_I_0"/>
|
||||
<value value="307" name="A8XX_DEBUGBUS_TP_GC_S_1_I_1"/>
|
||||
<value value="308" name="A8XX_DEBUGBUS_TP_GC_S_1_I_2"/>
|
||||
<value value="309" name="A8XX_DEBUGBUS_TP_GC_S_1_I_3"/>
|
||||
<value value="318" name="A8XX_DEBUGBUS_RB_GC_S_1_I_0"/>
|
||||
<value value="319" name="A8XX_DEBUGBUS_RB_GC_S_1_I_1"/>
|
||||
<value value="324" name="A8XX_DEBUGBUS_CCU_GC_S_1_I_0"/>
|
||||
<value value="325" name="A8XX_DEBUGBUS_CCU_GC_S_1_I_1"/>
|
||||
<value value="330" name="A8XX_DEBUGBUS_HLSQ_GC_S_1_I_0"/>
|
||||
<value value="331" name="A8XX_DEBUGBUS_HLSQ_GC_S_1_I_1"/>
|
||||
<value value="336" name="A8XX_DEBUGBUS_VFD_GC_S_1_I_0"/>
|
||||
<value value="337" name="A8XX_DEBUGBUS_VFD_GC_S_1_I_1"/>
|
||||
<value value="384" name="A8XX_DEBUGBUS_CP_GC_S_2_I_0"/>
|
||||
<value value="385" name="A8XX_DEBUGBUS_PC_BR_S_2_I_0"/>
|
||||
<value value="386" name="A8XX_DEBUGBUS_PC_BV_S_2_I_0"/>
|
||||
<value value="387" name="A8XX_DEBUGBUS_TESS_GC_S_2_I_0"/>
|
||||
<value value="388" name="A8XX_DEBUGBUS_TSEFE_GC_S_2_I_0"/>
|
||||
<value value="389" name="A8XX_DEBUGBUS_TSEBE_GC_S_2_I_0"/>
|
||||
<value value="390" name="A8XX_DEBUGBUS_RAS_GC_S_2_I_0"/>
|
||||
<value value="391" name="A8XX_DEBUGBUS_LRZ_BR_S_2_I_0"/>
|
||||
<value value="392" name="A8XX_DEBUGBUS_LRZ_BV_S_2_I_0"/>
|
||||
<value value="393" name="A8XX_DEBUGBUS_VFDP_GC_S_2_I_0"/>
|
||||
<value value="394" name="A8XX_DEBUGBUS_GPC_BR_S_2_I_0"/>
|
||||
<value value="395" name="A8XX_DEBUGBUS_GPC_BV_S_2_I_0"/>
|
||||
<value value="396" name="A8XX_DEBUGBUS_VPCFE_BR_S_2_I_0"/>
|
||||
<value value="397" name="A8XX_DEBUGBUS_VPCFE_BV_S_2_I_0"/>
|
||||
<value value="398" name="A8XX_DEBUGBUS_VPCBE_BR_S_2_I_0"/>
|
||||
<value value="399" name="A8XX_DEBUGBUS_VPCBE_BV_S_2_I_0"/>
|
||||
<value value="400" name="A8XX_DEBUGBUS_CCHE_GC_S_2_I_0"/>
|
||||
<value value="401" name="A8XX_DEBUGBUS_DBGC_GC_S_2_I_0"/>
|
||||
<value value="402" name="A8XX_DEBUGBUS_LARC_GC_S_2_I_0"/>
|
||||
<value value="403" name="A8XX_DEBUGBUS_RBBM_GC_S_2_I_0"/>
|
||||
<value value="404" name="A8XX_DEBUGBUS_CCRE_GC_S_2_I_0"/>
|
||||
<value value="405" name="A8XX_DEBUGBUS_CGC_GC_S_2_I_0"/>
|
||||
<value value="406" name="A8XX_DEBUGBUS_GMU_GC_S_2_I_0"/>
|
||||
<value value="407" name="A8XX_DEBUGBUS_SLICE_GC_S_2_I_0"/>
|
||||
<value value="408" name="A8XX_DEBUGBUS_HLSQ_SPTP_STAR_GC_S_2_I_0"/>
|
||||
<value value="416" name="A8XX_DEBUGBUS_USP_GC_S_2_I_0"/>
|
||||
<value value="417" name="A8XX_DEBUGBUS_USP_GC_S_2_I_1"/>
|
||||
<value value="422" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_0"/>
|
||||
<value value="423" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_1"/>
|
||||
<value value="424" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_2"/>
|
||||
<value value="425" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_3"/>
|
||||
<value value="434" name="A8XX_DEBUGBUS_TP_GC_S_2_I_0"/>
|
||||
<value value="435" name="A8XX_DEBUGBUS_TP_GC_S_2_I_1"/>
|
||||
<value value="436" name="A8XX_DEBUGBUS_TP_GC_S_2_I_2"/>
|
||||
<value value="437" name="A8XX_DEBUGBUS_TP_GC_S_2_I_3"/>
|
||||
<value value="446" name="A8XX_DEBUGBUS_RB_GC_S_2_I_0"/>
|
||||
<value value="447" name="A8XX_DEBUGBUS_RB_GC_S_2_I_1"/>
|
||||
<value value="452" name="A8XX_DEBUGBUS_CCU_GC_S_2_I_0"/>
|
||||
<value value="453" name="A8XX_DEBUGBUS_CCU_GC_S_2_I_1"/>
|
||||
<value value="458" name="A8XX_DEBUGBUS_HLSQ_GC_S_2_I_0"/>
|
||||
<value value="459" name="A8XX_DEBUGBUS_HLSQ_GC_S_2_I_1"/>
|
||||
<value value="464" name="A8XX_DEBUGBUS_VFD_GC_S_2_I_0"/>
|
||||
<value value="465" name="A8XX_DEBUGBUS_VFD_GC_S_2_I_1"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a8xx_usptp_id">
|
||||
<value value="0" name="A8XX_uSPTP0"/>
|
||||
<value value="1" name="A8XX_uSPTP1"/>
|
||||
<value value="15" name="A8XX_SPTOP"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a8xx_tex_swiz">
|
||||
<value name="A8XX_SWIZ_IDENTITY" value="0"/>
|
||||
<value name="A8XX_SWIZ_ZERO" value="1"/>
|
||||
<value name="A8XX_SWIZ_ONE" value="2"/>
|
||||
<value name="A8XX_SWIZ_X" value="3"/>
|
||||
<value name="A8XX_SWIZ_Y" value="4"/>
|
||||
<value name="A8XX_SWIZ_Z" value="5"/>
|
||||
<value name="A8XX_SWIZ_W" value="6"/>
|
||||
</enum>
|
||||
|
||||
</database>
|
||||
|
|
@ -11,6 +11,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<value name="A5XX" value="5"/>
|
||||
<value name="A6XX" value="6"/>
|
||||
<value name="A7XX" value="7"/>
|
||||
<value name="A8XX" value="8"/>
|
||||
</enum>
|
||||
|
||||
<enum name="adreno_pa_su_sc_draw">
|
||||
|
|
|
|||
|
|
@ -6,103 +6,102 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<import file="adreno/adreno_common.xml"/>
|
||||
|
||||
<enum name="vgt_event_type" varset="chip">
|
||||
<value name="VS_DEALLOC" value="0"/>
|
||||
<value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>
|
||||
<value name="VS_DONE_TS" value="2"/>
|
||||
<value name="PS_DONE_TS" value="3"/>
|
||||
<value name="VS_DEALLOC" value="0x00" variants="A2XX-A5XX"/>
|
||||
<value name="PS_DEALLOC" value="0x01" variants="A2XX-A5XX"/>
|
||||
<value name="VS_DONE_TS" value="0x02" variants="A2XX-A5XX"/>
|
||||
<value name="PS_DONE_TS" value="0x03" variants="A2XX-A5XX"/>
|
||||
<doc>
|
||||
Flushes dirty data from UCHE, and also writes a GPU timestamp to
|
||||
the address if one is provided.
|
||||
</doc>
|
||||
<value name="CACHE_FLUSH_TS" value="4"/>
|
||||
<value name="CONTEXT_DONE" value="5"/>
|
||||
<value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/>
|
||||
<value name="VIZQUERY_START" value="7" variants="A2XX"/>
|
||||
<value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
|
||||
<value name="VIZQUERY_END" value="8" variants="A2XX"/>
|
||||
<value name="SC_WAIT_WC" value="9" variants="A2XX"/>
|
||||
<value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX-"/>
|
||||
<value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX-"/>
|
||||
<value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX-"/>
|
||||
<value name="CACHE_FLUSH_TS" value="0x04"/>
|
||||
<value name="CONTEXT_DONE" value="0x05"/>
|
||||
<value name="CACHE_FLUSH" value="0x06" variants="A2XX-A4XX"/>
|
||||
<value name="VIZQUERY_START" value="0x07" variants="A2XX"/>
|
||||
<value name="HLSQ_FLUSH" value="0x07" variants="A3XX-A4XX"/>
|
||||
<value name="VIZQUERY_END" value="0x08" variants="A2XX"/>
|
||||
<value name="SC_WAIT_WC" value="0x09" variants="A2XX"/>
|
||||
<value name="WRITE_PRIMITIVE_COUNTS" value="0x09" variants="A6XX-"/>
|
||||
<value name="START_PRIMITIVE_CTRS" value="0x0b" variants="A6XX-"/>
|
||||
<value name="STOP_PRIMITIVE_CTRS" value="0x0c" variants="A6XX-"/>
|
||||
<!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
|
||||
<value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
|
||||
<value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
|
||||
<value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/>
|
||||
<value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
|
||||
<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
|
||||
<value name="RST_PIX_CNT" value="0x0d" variants="A2XX-A4XX"/>
|
||||
<value name="RST_VTX_CNT" value="0x0e" variants="A2XX-A4XX"/>
|
||||
<value name="TILE_FLUSH" value="0x0f" variants="A2XX-A4XX"/>
|
||||
<value name="STAT_EVENT" value="0x10" variants="A2XX-A4XX"/>
|
||||
<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="0x14" variants="A2XX-A4XX"/>
|
||||
<doc>
|
||||
If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed
|
||||
sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main
|
||||
memory, skipping UCHE.
|
||||
</doc>
|
||||
<value name="ZPASS_DONE" value="21"/>
|
||||
<value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
|
||||
<value name="ZPASS_DONE" value="0x15"/>
|
||||
<value name="CACHE_FLUSH_AND_INV_EVENT" value="0x16" variants="A2XX"/>
|
||||
|
||||
<doc>
|
||||
Writes the GPU timestamp to the address that follows, once RB
|
||||
access and flushes are complete.
|
||||
</doc>
|
||||
<value name="RB_DONE_TS" value="22" variants="A3XX-"/>
|
||||
<value name="RB_DONE_TS" value="0x16" variants="A3XX-"/>
|
||||
|
||||
<value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/>
|
||||
<value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/>
|
||||
<value name="VS_FETCH_DONE" value="27"/>
|
||||
<value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/>
|
||||
<value name="PERFCOUNTER_START" value="0x17" variants="A2XX-A4XX"/>
|
||||
<value name="PERFCOUNTER_STOP" value="0x18" variants="A2XX-A4XX"/>
|
||||
<value name="VS_FETCH_DONE" value="0x1b" variants="A2XX-A5XX"/>
|
||||
<value name="FACENESS_FLUSH" value="0x1c" variants="A2XX-A4XX"/>
|
||||
|
||||
<!-- a5xx events -->
|
||||
<value name="WT_DONE_TS" value="8" variants="A5XX-"/>
|
||||
<value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/>
|
||||
<value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/>
|
||||
<value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/>
|
||||
<value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/>
|
||||
<value name="FLUSH_SO_0" value="17" variants="A5XX-"/>
|
||||
<value name="FLUSH_SO_1" value="18" variants="A5XX-"/>
|
||||
<value name="FLUSH_SO_2" value="19" variants="A5XX-"/>
|
||||
<value name="FLUSH_SO_3" value="20" variants="A5XX-"/>
|
||||
<value name="WT_DONE_TS" value="0x08" variants="A5XX-A6XX"/>
|
||||
<value name="START_FRAGMENT_CTRS" value="0x0d" variants="A5XX-"/>
|
||||
<value name="STOP_FRAGMENT_CTRS" value="0x0e" variants="A5XX-"/>
|
||||
<value name="START_COMPUTE_CTRS" value="0x0f" variants="A5XX-"/>
|
||||
<value name="STOP_COMPUTE_CTRS" value="0x10" variants="A5XX-"/>
|
||||
<value name="FLUSH_SO_0" value="0x11" variants="A5XX-"/>
|
||||
<value name="FLUSH_SO_1" value="0x12" variants="A5XX-"/>
|
||||
<value name="FLUSH_SO_2" value="0x13" variants="A5XX-"/>
|
||||
<value name="FLUSH_SO_3" value="0x14" variants="A5XX-"/>
|
||||
|
||||
<doc>
|
||||
Invalidates depth attachment data from the CCU. We assume this
|
||||
happens in the last stage.
|
||||
</doc>
|
||||
<value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/>
|
||||
<value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-A6XX"/>
|
||||
|
||||
<doc>
|
||||
Invalidates color attachment data from the CCU. We assume this
|
||||
happens in the last stage.
|
||||
</doc>
|
||||
<value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/>
|
||||
<value name="PC_CCU_INVALIDATE_COLOR" value="0x19" variants="A5XX-A6XX"/>
|
||||
|
||||
<doc>
|
||||
Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
|
||||
along with its registers, would be better named RESOLVE).
|
||||
</doc>
|
||||
<value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
|
||||
<value name="PC_CCU_RESOLVE_TS" value="0x1a" variants="A6XX"/>
|
||||
|
||||
<doc>
|
||||
Flushes depth attachment data from the CCU. We assume this
|
||||
happens in the last stage.
|
||||
</doc>
|
||||
<value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/>
|
||||
<value name="PC_CCU_FLUSH_DEPTH_TS" value="0x1c" variants="A5XX-A6XX"/>
|
||||
|
||||
<doc>
|
||||
Flushes color attachment data from the CCU. We assume this
|
||||
happens in the last stage.
|
||||
</doc>
|
||||
<value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/>
|
||||
<value name="PC_CCU_FLUSH_COLOR_TS" value="0x1d" variants="A5XX-A6XX"/>
|
||||
|
||||
<doc>
|
||||
2D blit to resolve GMEM to system memory (skipping CCU) at the
|
||||
end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
|
||||
more general blitting.
|
||||
Triggers a resolve (GMEM to sysmem) or unresolve (sysmem to
|
||||
GMEM) or clear blit, depending on CCU programming.
|
||||
</doc>
|
||||
<value name="BLIT" value="30" variants="A5XX-"/>
|
||||
<value name="CCU_RESOLVE" value="0x1e" variants="A5XX-"/>
|
||||
|
||||
<doc>
|
||||
Flip between the primary and secondary LRZ buffers. This is used
|
||||
for concurrent binning, so that BV can write to one buffer while
|
||||
BR reads from the other.
|
||||
</doc>
|
||||
<value name="LRZ_FLIP_BUFFER" value="36" variants="A7XX"/>
|
||||
<value name="LRZ_FLIP_BUFFER" value="0x24" variants="A7XX-"/>
|
||||
|
||||
<doc>
|
||||
Clears based on GRAS_LRZ_CNTL configuration, could clear
|
||||
|
|
@ -115,44 +114,46 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
CUR_DIR_UNSET = 0x3
|
||||
Clear of direction means setting the direction to CUR_DIR_UNSET.
|
||||
</doc>
|
||||
<value name="LRZ_CLEAR" value="37" variants="A5XX-"/>
|
||||
<value name="LRZ_CLEAR" value="0x25" variants="A5XX-"/>
|
||||
|
||||
<value name="LRZ_FLUSH" value="38" variants="A5XX-"/>
|
||||
<value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
|
||||
<value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
|
||||
<value name="LRZ_CACHE_INVALIDATE" value="40" variants="A7XX"/>
|
||||
<value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/>
|
||||
<value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
|
||||
<value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
|
||||
<value name="VSC_BINNING_START" value="44" variants="A5XX-"/>
|
||||
<value name="VSC_BINNING_END" value="45" variants="A5XX-"/>
|
||||
<value name="LRZ_FLUSH_INVALIDATE" value="0x26" variants="A5XX-A6XX"/>
|
||||
<value name="LRZ_CACHE_FLUSH" value="0x26" variants="A7XX-"/>
|
||||
<value name="BLIT_OP_FILL_2D" value="0x27" variants="A5XX-A6XX"/>
|
||||
<value name="BLIT_OP_COPY_2D" value="0x28" variants="A5XX-A6XX"/>
|
||||
<value name="LRZ_CACHE_INVALIDATE" value="0x28" variants="A7XX-"/>
|
||||
<value name="LRZ_Q_CACHE_INVALIDATE" value="0x29" variants="A7XX-"/>
|
||||
<value name="BLIT_OP_SCALE_2D" value="0x2a" variants="A5XX-"/>
|
||||
<value name="CONTEXT_DONE_2D" value="0x2b" variants="A5XX-"/>
|
||||
<value name="VSC_BINNING_START" value="0x2c" variants="A5XX-"/>
|
||||
<value name="VSC_BINNING_END" value="0x2d" variants="A5XX-"/>
|
||||
|
||||
<!-- a6xx events -->
|
||||
<doc>
|
||||
Invalidates UCHE.
|
||||
</doc>
|
||||
<value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
|
||||
<value name="CACHE_INVALIDATE" value="0x31" variants="A6XX"/>
|
||||
|
||||
<value name="LABEL" value="63" variants="A6XX-"/>
|
||||
<value name="DEBUG_LABEL" value="0x3f" variants="A6XX-"/>
|
||||
|
||||
<!-- note, some of these are the same as a6xx, just named differently -->
|
||||
|
||||
<doc> Doesn't seem to do anything </doc>
|
||||
<value name="DUMMY_EVENT" value="1" variants="A7XX"/>
|
||||
<value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/>
|
||||
<value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/>
|
||||
<value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/>
|
||||
<value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/>
|
||||
<value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/>
|
||||
<value name="CCU_RESOLVE" value="30" variants="A7XX"/>
|
||||
<value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/>
|
||||
<value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/>
|
||||
<value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/>
|
||||
<value name="CACHE_RESET" value="48" variants="A7XX"/>
|
||||
<value name="CACHE_CLEAN" value="49" variants="A7XX"/>
|
||||
<value name="DUMMY_EVENT" value="0x01" variants="A7XX-"/>
|
||||
<value name="CCU_INVALIDATE_DEPTH" value="0x18" variants="A7XX-"/>
|
||||
<value name="CCU_INVALIDATE_COLOR" value="0x19" variants="A7XX-"/>
|
||||
<value name="CCU_RESOLVE_CLEAN" value="0x1a" variants="A7XX-"/>
|
||||
<value name="CCU_FLUSH_DEPTH" value="0x1c" variants="A7XX-"/>
|
||||
<value name="CCU_FLUSH_COLOR" value="0x1d" variants="A7XX-"/>
|
||||
<value name="CCU_END_RESOLVE_GROUP" value="0x1f" variants="A7XX-"/>
|
||||
<value name="CCU_CLEAN_DEPTH" value="0x20" variants="A7XX-"/>
|
||||
<value name="CCU_CLEAN_COLOR" value="0x21" variants="A7XX-"/>
|
||||
<value name="CACHE_RESET" value="0x30" variants="A7XX-"/>
|
||||
<value name="CACHE_CLEAN" value="0x31" variants="A7XX-"/>
|
||||
<!-- TODO: deal with name conflicts with other gens -->
|
||||
<value name="CACHE_FLUSH7" value="50" variants="A7XX"/>
|
||||
<value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/>
|
||||
<value name="CACHE_FLUSH7" value="0x32" variants="A7XX-"/>
|
||||
<value name="CACHE_INVALIDATE7" value="0x33" variants="A7XX-"/>
|
||||
<value name="DEPTH_BUFFER_FLIP" value="0x3d" variants="A8XX-"/>
|
||||
<value name="CCH_FAST_CLEAR_CLEAN" value="0x1b" variants="A8XX-"/>
|
||||
</enum>
|
||||
|
||||
<enum name="pc_di_primtype">
|
||||
|
|
@ -310,11 +311,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
|
||||
<value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
|
||||
<doc>generate a VS|PS_done event</doc>
|
||||
<value name="CP_EVENT_WRITE_SHD" value="0x58"/>
|
||||
<value name="CP_EVENT_WRITE_SHD" value="0x58" variants="A2XX"/>
|
||||
<doc>generate a cache flush done event</doc>
|
||||
<value name="CP_EVENT_WRITE_CFL" value="0x59"/>
|
||||
<value name="CP_EVENT_WRITE_CFL" value="0x59" variants="A2XX"/>
|
||||
<doc>generate a z_pass done event</doc>
|
||||
<value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
|
||||
<value name="CP_EVENT_WRITE_ZPD" value="0x5b" variants="A2XX"/>
|
||||
<doc>
|
||||
not sure the real name, but this seems to be what is used for
|
||||
opencl, instead of CP_DRAW_INDX..
|
||||
|
|
@ -335,9 +336,9 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<doc>load constant into chip and to memory</doc>
|
||||
<value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/>
|
||||
<doc>load sequencer instruction memory (pointer-based)</doc>
|
||||
<value name="CP_IM_LOAD" value="0x27"/>
|
||||
<value name="CP_IM_LOAD" value="0x27" variants="A2XX"/>
|
||||
<doc>load sequencer instruction memory (code embedded in packet)</doc>
|
||||
<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
|
||||
<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b" variants="A2XX"/>
|
||||
<doc>load constants from a location in memory</doc>
|
||||
<value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
|
||||
<doc>selective invalidation of state pointers</doc>
|
||||
|
|
@ -662,6 +663,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/>
|
||||
|
||||
<value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/>
|
||||
|
||||
<value name="CP_SKIP_IB_MODE" value="0x27" variants="A7XX-"/>
|
||||
|
||||
<value name="CP_MEMORY_MAP_UPDATE" value="0x58" variants="A8XX-"/>
|
||||
|
||||
<value name="CP_BARRIER" value="0x59" variants="A8XX-"/>
|
||||
</enum>
|
||||
|
||||
|
||||
|
|
@ -1800,49 +1807,73 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
<value value="6" name="RM6_BIN_RESOLVE"/>
|
||||
<value value="7" name="RM6_BIN_RENDER_END"/>
|
||||
<value value="8" name="RM6_COMPUTE"/>
|
||||
<value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
|
||||
<value value="12" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
|
||||
|
||||
<!--
|
||||
These values come from a6xx_set_marker() in the
|
||||
downstream kernel, and they can only be set by the kernel
|
||||
-->
|
||||
<value value="0xd" name="RM6_IB1LIST_START"/>
|
||||
<value value="0xe" name="RM6_IB1LIST_END"/>
|
||||
<value value="13" name="RM6_IB1LIST_START"/>
|
||||
<value value="14" name="RM6_IB1LIST_END"/>
|
||||
<value value="15" name="RM7_BIN_VISIBILITY_END"/>
|
||||
|
||||
<!-- new in a8xx: -->
|
||||
<value value="32" name="RM8_DEPTH_PASS_START"/>
|
||||
<value value="33" name="RM8_DEPTH_PASS_END"/>
|
||||
<value value="34" name="RM8_SET_RENDER_TARGET"/>
|
||||
<value value="35" name="RM8_PGMEM_ON"/>
|
||||
<value value="36" name="RM8_PGMEM_OFF"/>
|
||||
</enum>
|
||||
<reg32 offset="0" name="0">
|
||||
<!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
|
||||
<bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/>
|
||||
<stripe varset="chip" variants="A6XX-A7XX">
|
||||
<reg32 offset="0" name="0">
|
||||
<!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
|
||||
<bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/>
|
||||
|
||||
<bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
|
||||
<!-- used by preemption to determine if GMEM needs to be saved or not -->
|
||||
<bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
|
||||
|
||||
<bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/>
|
||||
<bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
|
||||
<!-- used by preemption to determine if GMEM needs to be saved or not -->
|
||||
<bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
|
||||
|
||||
<!--
|
||||
CP_SET_MARKER is used with these bits to create a
|
||||
critical section around a workaround for ray tracing.
|
||||
The workaround happens after BVH building, and appears
|
||||
to invalidate the RTU's BVH node cache. It makes sure
|
||||
that only one of BR/BV/LPAC is executing the
|
||||
workaround at a time, and no draws using RT on BV/LPAC
|
||||
are executing while the workaround is executed on BR (or
|
||||
vice versa, that no draws on BV/BR using RT are executed
|
||||
while the workaround executes on LPAC), by
|
||||
hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS.
|
||||
The blob usage is:
|
||||
|
||||
CP_SET_MARKER(RT_WA_START)
|
||||
... workaround here ...
|
||||
CP_SET_MARKER(RT_WA_END)
|
||||
...
|
||||
CP_SET_MARKER(SHADER_USES_RT)
|
||||
CP_DRAW_INDX(...) or CP_EXEC_CS(...)
|
||||
-->
|
||||
<bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/>
|
||||
<bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/>
|
||||
<bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/>
|
||||
</reg32>
|
||||
<bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/>
|
||||
|
||||
|
||||
<!--
|
||||
CP_SET_MARKER is used with these bits to create a
|
||||
critical section around a workaround for ray tracing.
|
||||
The workaround happens after BVH building, and appears
|
||||
to invalidate the RTU's BVH node cache. It makes sure
|
||||
that only one of BR/BV/LPAC is executing the
|
||||
workaround at a time, and no draws using RT on BV/LPAC
|
||||
are executing while the workaround is executed on BR (or
|
||||
vice versa, that no draws on BV/BR using RT are executed
|
||||
while the workaround executes on LPAC), by
|
||||
hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS.
|
||||
The blob usage is:
|
||||
|
||||
|
||||
CP_SET_MARKER(RT_WA_START)
|
||||
... workaround here ...
|
||||
CP_SET_MARKER(RT_WA_END)
|
||||
...
|
||||
CP_SET_MARKER(SHADER_USES_RT)
|
||||
CP_DRAW_INDX(...) or CP_EXEC_CS(...)
|
||||
-->
|
||||
<bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/>
|
||||
<bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/>
|
||||
<bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/>
|
||||
</reg32>
|
||||
</stripe>
|
||||
<stripe varset="chip" variants="A8XX-">
|
||||
<reg32 offset="0" name="0">
|
||||
<!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
|
||||
<bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/>
|
||||
<bitfield name="MODE" low="0" high="6" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
|
||||
<bitfield name="USES_GMEM" pos="7" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
|
||||
<bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/>
|
||||
<!-- idk if the RT w/a fields apply to a8xx as well -->
|
||||
</reg32>
|
||||
</stripe>
|
||||
</domain>
|
||||
|
||||
<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
|
||||
|
|
@ -2066,6 +2097,14 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
payload *and* skipsaverestore is set. This is
|
||||
expected to restore static register values not
|
||||
saved when skipsaverestore is set.
|
||||
|
||||
On BV, a skipsaverestore preemption is triggered
|
||||
and this preamble type is executed whenever a
|
||||
CP_THREAD_CONTROL that synchronizes threads
|
||||
happens. This can be explicitly via
|
||||
SYNC_THREADS, or implicitly when the value of
|
||||
CONCURRENT_BIN_DISABLE changes from the previous
|
||||
thread control.
|
||||
</doc>
|
||||
</value>
|
||||
<value name="POSTAMBLE_AMBLE_TYPE" value="2">
|
||||
|
|
@ -2308,5 +2347,99 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
</reg32>
|
||||
</domain>
|
||||
|
||||
<domain name="CP_RESOURCE_LIST" width="32">
|
||||
<doc>
|
||||
A7xx introduces the "resource table" which is managed by
|
||||
CP_RESOURCE_LIST. It is used to synchronize BR and BV access
|
||||
to resources such as LRZ buffers.
|
||||
|
||||
The resource table consists of resources that are in-use by BR.
|
||||
Each "resource" has a base address, which is
|
||||
usually a pointer but is treated by the HW as an opaque handle,
|
||||
a read/write bit, and a timestamp when it was last used.
|
||||
Resources are removed from the table upon event completion when
|
||||
a special CP_EVENT_WRITE::CLEAR_RENDER_RESOURCE bit is set, which
|
||||
will remove all resources with a timestamp up to the current
|
||||
timestamp.
|
||||
|
||||
CP_RESOURCE_LIST first specifies a list of BV resources. For
|
||||
each BV resource, the HW will check if there is a corresponding
|
||||
BR resource in the table, and if at least one of the BV and BR
|
||||
resources is marked WRITE then it will stall until the BR
|
||||
resource is removed.
|
||||
|
||||
It then specifies a list of BR resources. These will be added to
|
||||
the resource table, unless there is an overflow in which case
|
||||
the designated overflow register will have bit 0 set. Overflow
|
||||
should cause the next binning pass to stall until BR is done,
|
||||
effectively disabling concurrent binning.
|
||||
|
||||
CP_RESOURCE_LIST must be executed by BV. BR resources are added
|
||||
by BV and removed by BR.
|
||||
|
||||
There is a separate table for "LRZ resources." These behave a
|
||||
bit differently: specifying an LRZ resource via BV_RES_LRZ
|
||||
stalls on any matching resource existing and then adds it to the
|
||||
table, making it both a BV and BR resource in one. There is a
|
||||
separate CLEAR_LRZ_RESOURCE bit for removing resources from the
|
||||
LRZ table, and it only removes one resource given by a base
|
||||
address passed to CP_EVENT_WRITE. Therefore timestamps are
|
||||
unnecessary.
|
||||
</doc>
|
||||
<reg32 offset="0" name="BV_COUNT" type="uint"/>
|
||||
<doc>
|
||||
What follows is a list of CP_BV_RESOURCE and then CP_RESOURCE_LIST_BR.
|
||||
</doc>
|
||||
</domain>
|
||||
|
||||
<domain name="CP_BV_RESOURCE" width="32">
|
||||
<doc>
|
||||
BV resources don't go in the table. Instead CP waits until any
|
||||
corresponding BR resources with the same base pointer are
|
||||
finished before the packet completes.
|
||||
</doc>
|
||||
<enum name="cp_bv_resource_encoding">
|
||||
<value value="0" name="BV_RES_DIRECT"/>
|
||||
<doc>
|
||||
INDIRECT resources are encoded as a 32b offset + 3b
|
||||
bindless base selector. The offset is added to the given
|
||||
BINDLESS_BASE pseudoregister and then the 64b value
|
||||
fetched there is used as the pointer.
|
||||
</doc>
|
||||
<value value="1" name="BV_RES_INDIRECT_READ"/>
|
||||
<value value="2" name="BV_RES_LRZ"/>
|
||||
<value value="3" name="BV_RES_INDIRECT_WRITE"/>
|
||||
</enum>
|
||||
<reg64 offset="0" name="0">
|
||||
<bitfield name="BASE_ADDR" low="1" high="61" shr="1" type="address"/>
|
||||
<bitfield name="WRITE" pos="0" type="boolean"/>
|
||||
<bitfield name="ENCODING" low="62" high="63" type="cp_bv_resource_encoding"/>
|
||||
</reg64>
|
||||
</domain>
|
||||
|
||||
<domain name="CP_RESOURCE_LIST_BR" width="32">
|
||||
<reg32 offset="0" name="0">
|
||||
<bitfield name="BR_COUNT" low="0" high="23" type="uint"/>
|
||||
<bitfield name="OVERFLOW_ONCHIP_ADDR" low="24" high="26"/>
|
||||
<bitfield name="OVERFLOW" pos="31" type="boolean"/>
|
||||
</reg32>
|
||||
<doc>
|
||||
What follows is a list of CP_BR_RESOURCE.
|
||||
</doc>
|
||||
</domain>
|
||||
|
||||
<domain name="CP_BR_RESOURCE" width="32">
|
||||
<enum name="cp_br_resource_encoding">
|
||||
<value value="0" name="BR_RES_DIRECT"/>
|
||||
<value value="2" name="BR_RES_INDIRECT_READ"/>
|
||||
<value value="3" name="BR_RES_INDIRECT_WRITE"/> <!-- set WRITE bit -->
|
||||
</enum>
|
||||
<reg64 offset="0" name="0">
|
||||
<bitfield name="BASE_ADDR" low="1" high="61" shr="1" type="address"/>
|
||||
<bitfield name="WRITE" pos="0" type="boolean"/>
|
||||
<bitfield name="ENCODING" low="62" high="63" type="cp_br_resource_encoding"/>
|
||||
</reg64>
|
||||
</domain>
|
||||
|
||||
</database>
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user