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venus: firmware: Correct assertion of reset bit on remote processor
Currently we use read/write_relaxed in combination with mb() to assert reset. This looks wrong because mb() after write_relaxed() will not order correctly load-update-store sequence. Correct this by use readl/writel which include memory barriers. Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
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@ -181,17 +181,15 @@ static int venus_shutdown_no_tz(struct venus_core *core)
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if (IS_V6(core)) {
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/* Assert the reset to XTSS */
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reg = readl_relaxed(wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
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reg = readl(wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
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reg |= WRAPPER_XTSS_SW_RESET_BIT;
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writel_relaxed(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
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writel(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
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} else {
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/* Assert the reset to ARM9 */
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reg = readl_relaxed(wrapper_base + WRAPPER_A9SS_SW_RESET);
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reg = readl(wrapper_base + WRAPPER_A9SS_SW_RESET);
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reg |= WRAPPER_A9SS_SW_RESET_BIT;
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writel_relaxed(reg, wrapper_base + WRAPPER_A9SS_SW_RESET);
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writel(reg, wrapper_base + WRAPPER_A9SS_SW_RESET);
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}
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/* Make sure reset is asserted before the mapping is removed */
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mb();
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iommu = core->fw.iommu_domain;
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