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drm/amdgpu: Only calculate register offset once in SOC15 RLC

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We can save some text by only calculating the register offset once
in a few of the SOC15 RLC register read/write macros.

add/remove: 0/0 grow/shrink: 3/69 up/down: 62/-1259 (-1197)
...
Total: Before=9896030, After=9894833, chg -0.01%

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tvrtko Ursulin 2026-04-24 13:50:03 +01:00 committed by Alex Deucher
parent 6eadd448d7
commit 1eedf2c84b
1 changed files with 27 additions and 20 deletions
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47
drivers/gpu/drm/amd/amdgpu/soc15_common.h
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@ -43,21 +43,25 @@
#define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \
adev->gfx.rlc.reg_funcs->rreg32(adev, reg, flag, hwip, inst)
#define WREG32_FIELD15(ip, idx, reg, field, val) \
__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
(__RREG32_SOC15_RLC__( \
adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
0, ip##_HWIP, idx) & \
~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
0, ip##_HWIP, idx)
#define WREG32_FIELD15(ip, idx, reg_name, field, val) \
do { \
u32 reg__ = adev->reg_offset[ip##_HWIP][idx][mm##reg_name##_BASE_IDX] + mm##reg_name; \
u32 val__ = __RREG32_SOC15_RLC__(reg__, 0, ip##_HWIP, idx); \
\
val__ &= ~REG_FIELD_MASK(reg_name, field); \
val__ |= (val) << REG_FIELD_SHIFT(reg_name, field); \
__WREG32_SOC15_RLC__(reg__, val__, 0, ip##_HWIP, idx); \
} while (0)
#define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \
__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
(__RREG32_SOC15_RLC__( \
adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
0, ip##_HWIP, idx) & \
~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \
0, ip##_HWIP, idx)
#define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \
do { \
u32 reg__ = adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name; \
u32 val__ = __RREG32_SOC15_RLC__(reg__, 0, ip##_HWIP, idx); \
\
val__ &= ~REG_FIELD_MASK(reg_name, field); \
val__ |= (val) << REG_FIELD_SHIFT(reg_name, field); \
__WREG32_SOC15_RLC__(reg__, val__, 0, ip##_HWIP, idx); \
} while (0)
#define RREG32_SOC15(ip, inst, reg) \
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
@ -177,12 +181,15 @@
WREG32_RLC_EX(prefix, target_reg, value, inst); \
} while (0)
#define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
(__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
AMDGPU_REGS_RLC, ip##_HWIP, idx) & \
~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
AMDGPU_REGS_RLC, ip##_HWIP, idx)
#define WREG32_FIELD15_RLC(ip, idx, reg_name, field, val) \
do { \
u32 reg__ = adev->reg_offset[ip##_HWIP][idx][mm##reg_name##_BASE_IDX] + mm##reg_name; \
u32 val__ = __RREG32_SOC15_RLC__(reg__, AMDGPU_REGS_RLC, ip##_HWIP, idx); \
\
val__ &= ~REG_FIELD_MASK(reg_name, field); \
val__ |= (val) << REG_FIELD_SHIFT(reg_name, field); \
__WREG32_SOC15_RLC__(reg__, val__, AMDGPU_REGS_RLC, ip##_HWIP, idx); \
} while (0)
#define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP, inst)