From 91d04c759c85f1fc2d3ed7d1b5bc1a7dbab87f92 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Feb 2023 16:43:21 +0100 Subject: [PATCH 1/9] dt-bindings: pinctrl: qcom,sm8350: add input-disable The SM8350 HDK8350 board uses input-disable property, so allow it: sm8350-hdk.dtb: pinctrl@f100000: lt9611-state: 'oneOf' conditional failed, one must be fixed: ... 'input-disable' does not match any of the regexes: 'pinctrl-[0-9]+' Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230201154321.276419-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml index 49a74f351e99..e13d50d6d388 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml @@ -109,6 +109,7 @@ $defs: bias-pull-down: true bias-pull-up: true drive-strength: true + input-disable: true input-enable: true output-high: true output-low: true From 792349083a7307bf34de26516bc047cfd5c6296b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:43 +0100 Subject: [PATCH 2/9] dt-bindings: pinctrl: qcom,msm8226: correct GPIO name pattern The MSM8226 TLMM pin controller has GPIOs 0-116, so correct the pattern to bring back missing 107-109. Acked-by: Rob Herring Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20230202104452.299048-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml index ab6672a4c8c1..59759a5742c4 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml @@ -56,7 +56,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 From 87b93dd1fbb23b9bbae461bb2c01f6d93c7524d9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:44 +0100 Subject: [PATCH 3/9] dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example The MSM8909 TLMM pin controller has GPIOs 0-112, so narrow the pattern and gpio-ranges in the example. Fixes: c249ec7ba1b1 ("dt-bindings: pinctrl: Add DT schema for qcom,msm8909-tlmm") Reviewed-by: Stephan Gerhold Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml index 449e6e34be61..85082adc1811 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml @@ -63,7 +63,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, qdsd_data3 ] @@ -127,7 +127,7 @@ examples: interrupts = ; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 117>; + gpio-ranges = <&tlmm 0 0 113>; interrupt-controller; #interrupt-cells = <2>; From a51c1f0244c84e482f1ceb4701c38aaa4b224baf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:45 +0100 Subject: [PATCH 4/9] dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example The SM6375 TLMM pin controller has GPIOs 0-155, so narrow the pattern and gpio-ranges in the example. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml index e4231d10d76f..66cef48ed59b 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml @@ -63,7 +63,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 @@ -134,7 +134,7 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 157>; + gpio-ranges = <&tlmm 0 0 157>; /* GPIOs + ufs_reset */ gpio-wo-subnode-state { pins = "gpio1"; From 913137a1cd1e792587e8ae2a43d31389fdbaddf6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:46 +0100 Subject: [PATCH 5/9] dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern The MSM8953 TLMM pin controller has GPIOs 0-141, so narrow the pattern. Acked-by: Rob Herring Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20230202104452.299048-5-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml index 6bcd52080801..ce219827ccc8 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -53,7 +53,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[01])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, qdsd_data3 ] From 5c7069712c9be01d1bf9061a7ef5ce78df0af0a5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:47 +0100 Subject: [PATCH 6/9] dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern The SDX55 TLMM pin controller has GPIOs 0-107, so narrow the pattern. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml index add3c7e64520..a40175258495 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -55,7 +55,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 From 174668bf5f6c2dd03441a4660e249cc5e2c78b95 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:48 +0100 Subject: [PATCH 7/9] dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs The MSM8994 TLMM pin controller has GPIOs 0-145, so narrow the pattern and reduce sizes of arrays with pins. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-7-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml index f4a8180f5959..0c4936fc35ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml @@ -34,10 +34,10 @@ properties: gpio-reserved-ranges: minItems: 1 - maxItems: 75 + maxItems: 73 gpio-line-names: - maxItems: 150 + maxItems: 146 patternProperties: "-state$": @@ -63,7 +63,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ] minItems: 1 From 6f4e10ffa8fbccf220f7c5c869e8373065b9ef7d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:49 +0100 Subject: [PATCH 8/9] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples Correct the number of GPIOs in gpio-ranges to match reality. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-8-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 2 +- Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index 56e058c315f7..cf561dff8893 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -131,6 +131,6 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 180>; + gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */ wakeup-parent = <&pdc>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml index e13d50d6d388..797242f68b1c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml @@ -130,7 +130,7 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 203>; + gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */ gpio-wo-subnode-state { pins = "gpio1"; From 315dffb843f75cec4458714f4d151d5775e797de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 3 Feb 2023 17:48:50 +0100 Subject: [PATCH 9/9] dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern Narrow the pattern of possible GPIO names for pin controllers: - SC7280 LPASS: GPIOs 0-14 - SM8250 LPASS: GPIOs 0-13 - SM8450 LPASS: GPIOs 0-22 - SC8280XP LPASS: GPIOs 0-18 Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230203164854.390080-1-krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20230203164854.390080-2-krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20230203164854.390080-3-krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20230203164854.390080-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 2 +- .../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 2 +- .../bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 2 +- .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml index f7ec8a4f664f..e51feb4c0700 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -59,7 +59,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9])$" + - pattern: "^gpio([0-9]|1[0-4])$" minItems: 1 maxItems: 15 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml index 9a3f1fb8c2f7..200b3b6ccd87 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml @@ -134,7 +134,7 @@ examples: clock-names = "core", "audio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&lpi_tlmm 0 0 18>; + gpio-ranges = <&lpi_tlmm 0 0 19>; dmic01-state { dmic01-clk-pins { diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml index bd45faa3f078..de9d8854c690 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml @@ -64,7 +64,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9])$" + - pattern: "^gpio([0-9]|1[0-3])$" minItems: 1 maxItems: 14 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml index 01a0a4a40ba5..6acaa42a3c1b 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -65,7 +65,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: - pattern: "^gpio([0-9]|[1-2][0-9])$" + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" function: enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,