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drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
Although we already strip 3D-specific flags from PIPE_CONTROL instructions when submitting to a compute engine, there are some additional flags that need to be removed when the platform as a whole lacks a 3D pipeline. Add those restrictions here. v2: - Replace LACKS_3D_PIPELINE checks with !HAS_3D_PIPELINE and add has_3d_pipeline to all platforms except PVC. (Lucas) Bspec: 47112 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220511060228.1179450-4-matthew.d.roper@intel.com
This commit is contained in:
Stuart Summers
Matt Roper
parent
fb289464f6
commit
1eb3133899
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@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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flags |= PIPE_CONTROL_CS_STALL;
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if (engine->class == COMPUTE_CLASS)
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flags &= ~PIPE_CONTROL_3D_FLAGS;
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if (!HAS_3D_PIPELINE(engine->i915))
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flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
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else if (engine->class == COMPUTE_CLASS)
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flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
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cs = intel_ring_begin(rq, 6);
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if (IS_ERR(cs))
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@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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flags |= PIPE_CONTROL_CS_STALL;
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if (engine->class == COMPUTE_CLASS)
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flags &= ~PIPE_CONTROL_3D_FLAGS;
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if (!HAS_3D_PIPELINE(engine->i915))
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flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
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else if (engine->class == COMPUTE_CLASS)
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flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
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if (!HAS_FLAT_CCS(rq->engine->i915))
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count = 8 + 4;
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@ -717,8 +721,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
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/* Wa_1409600907 */
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flags |= PIPE_CONTROL_DEPTH_STALL;
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if (rq->engine->class == COMPUTE_CLASS)
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flags &= ~PIPE_CONTROL_3D_FLAGS;
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if (!HAS_3D_PIPELINE(rq->engine->i915))
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flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
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else if (rq->engine->class == COMPUTE_CLASS)
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flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
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cs = gen12_emit_ggtt_write_rcs(cs,
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rq->fence.seqno,
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@ -310,8 +310,11 @@
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#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
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#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
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/* 3D-related flags can't be set on compute engine */
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#define PIPE_CONTROL_3D_FLAGS (\
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/*
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* 3D-related flags that can't be set on _engines_ that lack access to the 3D
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* pipeline (i.e., CCS engines).
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*/
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#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
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PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
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PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
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PIPE_CONTROL_TILE_CACHE_FLUSH | \
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@ -322,6 +325,14 @@
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PIPE_CONTROL_VF_CACHE_INVALIDATE | \
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PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
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/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
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#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
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PIPE_CONTROL_3D_ENGINE_FLAGS | \
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PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
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PIPE_CONTROL_FLUSH_ENABLE | \
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
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PIPE_CONTROL_DC_FLUSH_ENABLE)
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#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
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#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
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/* Opcodes for MI_MATH_INSTR */
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@ -1405,6 +1405,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
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#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
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/* i915_gem.c */
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void i915_gem_init_early(struct drm_i915_private *dev_priv);
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void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
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@ -171,6 +171,7 @@
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.display.overlay_needs_physical = 1, \
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.display.has_gmch = 1, \
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.gpu_reset_clobbers_display = true, \
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.has_3d_pipeline = 1, \
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.hws_needs_physical = 1, \
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.unfenced_needs_alignment = 1, \
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.platform_engine_mask = BIT(RCS0), \
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@ -190,6 +191,7 @@
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.display.has_overlay = 1, \
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.display.overlay_needs_physical = 1, \
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.display.has_gmch = 1, \
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.has_3d_pipeline = 1, \
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.gpu_reset_clobbers_display = true, \
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.hws_needs_physical = 1, \
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.unfenced_needs_alignment = 1, \
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@ -232,6 +234,7 @@ static const struct intel_device_info i865g_info = {
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.display.has_gmch = 1, \
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.gpu_reset_clobbers_display = true, \
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.platform_engine_mask = BIT(RCS0), \
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.has_3d_pipeline = 1, \
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.has_snoop = true, \
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.has_coherent_ggtt = true, \
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.dma_mask_size = 32, \
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@ -323,6 +326,7 @@ static const struct intel_device_info pnv_m_info = {
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.display.has_gmch = 1, \
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.gpu_reset_clobbers_display = true, \
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.platform_engine_mask = BIT(RCS0), \
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.has_3d_pipeline = 1, \
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.has_snoop = true, \
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.has_coherent_ggtt = true, \
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.dma_mask_size = 36, \
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@ -374,6 +378,7 @@ static const struct intel_device_info gm45_info = {
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.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
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.display.has_hotplug = 1, \
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.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
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.has_3d_pipeline = 1, \
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.has_snoop = true, \
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.has_coherent_ggtt = true, \
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/* ilk does support rc6, but we do not implement [power] contexts */ \
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@ -405,6 +410,7 @@ static const struct intel_device_info ilk_m_info = {
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.display.has_hotplug = 1, \
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.display.fbc_mask = BIT(INTEL_FBC_A), \
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.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
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.has_3d_pipeline = 1, \
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.has_coherent_ggtt = true, \
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.has_llc = 1, \
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.has_rc6 = 1, \
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@ -456,6 +462,7 @@ static const struct intel_device_info snb_m_gt2_info = {
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.display.has_hotplug = 1, \
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.display.fbc_mask = BIT(INTEL_FBC_A), \
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.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
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.has_3d_pipeline = 1, \
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.has_coherent_ggtt = true, \
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.has_llc = 1, \
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.has_rc6 = 1, \
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@ -692,6 +699,7 @@ static const struct intel_device_info skl_gt4_info = {
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.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
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BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
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BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
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.has_3d_pipeline = 1, \
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.has_64bit_reloc = 1, \
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.display.has_ddi = 1, \
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.display.has_fpga_dbg = 1, \
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@ -1005,6 +1013,7 @@ static const struct intel_device_info adl_p_info = {
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.graphics.rel = 50, \
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XE_HP_PAGE_SIZES, \
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.dma_mask_size = 46, \
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.has_3d_pipeline = 1, \
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.has_64bit_reloc = 1, \
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.has_flat_ccs = 1, \
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.has_global_mocs = 1, \
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@ -1080,6 +1089,7 @@ static const struct intel_device_info ats_m_info = {
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#define XE_HPC_FEATURES \
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XE_HP_FEATURES, \
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.dma_mask_size = 52, \
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.has_3d_pipeline = 0, \
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.has_l3_ccs_read = 1
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__maybe_unused
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@ -143,6 +143,7 @@ enum intel_ppgtt_type {
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func(needs_compact_pt); \
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func(gpu_reset_clobbers_display); \
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func(has_reset_engine); \
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func(has_3d_pipeline); \
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func(has_4tile); \
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func(has_flat_ccs); \
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func(has_global_mocs); \
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